3. DAUGHTERBOARD DESCRIPTION

3.1 Block Diagram

The block diagram in Figure 3-1 shows the major hardware components including optional flash with a hypothetical FPGA program, a possible selection of A/D and D/C converters and amplifiers that demonstrates the use of all these components.

Figure 3-1. AED-300 Block Diagram

The following subsections reference to this block diagram and the schematics in Appendix A.

3.2 FPGA Functions

The FPGA is referenced as U3 on the daughterboard when a Spartan FPGA is mounted with a PQ 208 package . All of the signals in the EVM external interfaces feed into the FPGA. The FPGA is also connected to the control lines on the flash, and some pins are wired to the breadboard are which can connect to the digital lines of converters. Alternately, the larger exterior footprint referenced as U1 can be used for larger, optional FPGAs with a PQ/HQ 240 package.

The 24 digital I/O are not shown in Figure 3-1. These connect from the FPGA to the 74LVTH245 transceivers (U19 and U20), and then to a 40-pin connector (J15).

The FPGA controls the interface between the EVM board and the daughterboard. All signal traffic goes through the FPGA except for the address and data lines driving the flash. Only the control lines on the flash are wired to the FPGA. The FPGA can use the address lines from the EVM to decode reads/writes to the flash, to the digital I/O, and to the mixed signal area.

On power-up, the FPGA configuration is loaded automatically from the serial PROM (U2) or the configuration flash (U9 and/or U10). The FPGA program can then direct the flash to boot-load the DSP. This operation is covered in more detail in the software section of the manual.

The signals from the FPGA to the mixed signal area can control A/Ds and D/A as well as receive digitized data samples from the A/Ds. The converter clocks can be derived from any of the clocks development board supplied to the daughterboard, from a digital I/O pin or from a oscillator mounted in the breadboard area. Digital I/O number 1 (D_CNTL1, J15 pin 39) is specifically designed for this purpose.

Another useful function is preprocessing of the A/D samples before sending them to the DSP. This can greatly reduce the load on the DSP. Processor load can also be reduced by using the DMA to retrieve the samples from the FPGA and writing them directly to memory. The FPGA can control an external interrupt and read the DMA control which facilitates the DMA interface. An example of this can be seen in the example program.

In addition, all of the lines for the DSP serial ports, DSP clocks, DMA control lines, and the control/status lines from the EVM are available at the FPGA pins.

3.3 Digital Connections in the Mixed Signal Mounting Area

Each pad on the digital side (nearest the FPGA) is designed to allow it to be easily wired to digital ground, to digital 5.0 or 3.3 volt supplies or to an FPGA signal I/O pin with 0603 surface mount jumpers. The pads can have 0603 surface mount pull-up/pull-down resistors, bypass capacitors, or series ferrite beads added. The pad can also be wired directly to the desired location using #28 or 30 wire.

3.4 Analog Connections in the Mixed Signal Mounting Area

Each pad on the analog side (nearest the breadboard area) is designed to allow it to be easily wired to analog ground, to analog +5 volt supply, to one of two reference voltage buses or to through a series component to a wiring hole with 0603 surface mount jumpers or components. The pads can have 0603 surface mount pull-up/pull-down resistors, bypass capacitors, or series ferrite beads added. The pad or the additional wiring hole can also be wired directly to the desired location using #28 or 30 wire.

Additionally, the daughterboard has a provision to mount a regulator to provide a low voltage analog supply. This supply may be connected to either analog reference bus. The regulator is supplied with +5 Volts, and regulators may be purchased for several different common voltages.

3.5 Digital Buffers

The digital transceivers, U19 and U20, are 74LVTH245 and 74LVTH244 respectively. They buffer the digital signals between the FPGA and the connector J15. U19 buffers I/O numbers 9-16 ; U20 buffers I/O numbers 1-8 (odd numbers are input, even are output). They can support digital I/O up to 100 MHz. The buffers can be enabled or disabled all together, and the directions can be set by the FPGA 9-16 group of eight. Optionally, the 1-8 group can have a 74LVTH245 substituted for U20 to give two groups of 8 with directional control.

3.6 Reference Supplies

Three reference supplies are provided, 4.096 V, 2.048 V, and 1.024 V. The 2.048-V and 1.024-V supplies are adjusted with pots R20 and R24. Care must be taken in using these supplies not to overload or put the supply out of calibration. The 4.096-V supply is regulated with a reference diode and can produce 20 mA. The 2.048-V and 1.024-V supplies are not regulated; use of these supplies must be limited to 0.1 mA and must not vary dynamically. If the loads on the references, are dynamically varying, a buffer amplifier should be used on each one.

3.7 Flash Memory (optional)

The flash memory chips, AM29LV400B, are referenced as U13 and U14. These do not come standard on the board, but can be purchased as options. These are each 4.0 Megabit, CMOS, 3.3-V only, boot-sector flash memory. They can be written to directly with the DSP. The FPGA is used to insert wait states into the read/write cycles. The flash can be used to boot-load the DSP on power-up. The example program provided does not provide for the interface to the Flash memory. This function can be programmed into the FPGA by the user. Refer to the AM29LV400B data sheet for details on operation.

3.8 Amplifiers and Transformers (optional)

Two dual channel amplifiers are referenced as U100, and U200. The dual sections may be used separately or to give a differential output. The input analog signal can be directly wired to each of the inverting and non-inverting inputs to the two amplifiers, applied through the breadboard area, or applied through a transformer. With the appropriate connectors are installed, the signal can be connected in through J5 through J6 or J16. A reference voltage may be applied to bias the amplifier.

Many different amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-2 shows two non-inverting configurations. The x in the component identification indicates the amplifier used, for example U100a has R100 as the feedback resistor. For U100b, R100 becomes R101. See Appendix C for details of the component identification suffix conventions in multi-pad components like Rx14.

Figure 3-3 shows two inverting configurations similar to Figure 3-2. The Biased Inverting Amplifier is very useful in converting a +/- V signal into a biased signal suitable for input to A/D converters.

Combining the Biased Unity Gain Buffer with the Biased Inverting Amplifier and driving both with the same input signal results in a singled ended input amplifier with differential biased output.

Two single section amplifiers are referenced as U300 and U400. The analog signal can be wired directly to the inverting and non-inverting inputs to the two amplifiers, or applied through a transformer. With the appropriate connectors installed, the signal can be connected through J3 through J4 or J16. A reference voltage may be applied to bias the amplifier.

Many different output amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-4 shows two non-inverting configurations.

Figure 3-5 shows two inverting configurations. The Differential Input Amplifier is also useful as a single ended output amplifier for devices with differential signal output.

The outputs of all amplifiers may be connected to output through a transformer and connectors J5 and J8 or to the bread board area . See the schematic in Appendix A for details.

3.9 Breadboard Area

The breadboard area was designed for building custom analog circuitry. Adjacent to the breadboard area is J16 which provides 20 analog inputs and 8 analog outputs. The 20 analog inputs can be differential or single ended. In the differential mode, the negative side must be wired into the breadboard. In the single ended mode, each wire in the cable has a ground wire between it an the adjoining wire which is grounded with a zero-ohm jumper. The breadboard area was designed for using both through-hole and 50 mil surface-mount components. The breadboard has +/- 9 V available throughout.

Included in Appendix C are enlarged silkscreens and enlarged copper layout of the breadboard area. Because of the small size of components used, the silkscreens do not have all the component labels, but the enlarged silkscreens are complete. Enlargements are helpful for finding components and test points on the board, and are useful for laying out component placement in the planning stage.

3.10 External Interfaces

The required external interface is the connection to the target board through the expansion connectors. The daughterboard must be mounted directly on the connectors. No interconnect cable is used. Additionally, the FPGA JTAG connector may be used to connect the daughterboard to a host computer, usually a PC, through a JTAG cable to maintain the FPGA configuration. Usually, both digital and analog inputs and outputs are connected through the daughterboard as well.

3.10.1 Multi-platform Expansion Connectors

Two 80 pin connectors provide the interface between the DSP on the target board and the daughterboard. One expansion connector provides access to the DSP's asynchronous EMIF (External Memory Interface), and the other provides access to the DSP's peripherals and control/status signals. Both connectors also provide power to the daughterboard. Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the target board.⁽¹⁾

The expansion memory interface connector has a reference designator of J6 on the target and J9 on the daughterboard. The expansion peripheral interface connector is J7 on the target and J10 on the daughterboard. The pinouts are in Tables 3-1 and 3-2 respectively below. The connections on the daughterboard are listed. Of particular interest is the FPGA pin number which must be referenced in FPGA configurations in order the make the proper connections in the FPGA.

Table 3-1. Expansion Memory Interface

Table 3-2. Expansion Peripheral Interface

3.10.2 JTAG Port for FPGA Programming

The JTAG connector is a 14-pin single-row header that has a reference designator of J1 on the daughterboard. When using the JTAG Programmer to load the FPGA configurations directly (bypassing the SPROM or flash), the INIT pin on the FPGA must be pulled low. This is accomplished by placing a jumper between pins 1 and 2 on J1. The pin-out for J1 is shown in Table 3-3. The connection to the PC is intended to be made with the Xilinx download cable. The connection to the cable is also shown in Table 3-3. Also, the necessary signals are brought to this connector for using Xilinx's Hardware Debugger.

Table 3-3. JTAG Port Pin Description (AED-300)

3.10.3 Digital I/O Connector

The digital I/O connector is a 40-pin, 50 mil pitch, double-row connector designated J15; Figure 3-2 shows how this connector is positioned and oriented on the board. This connector has 24 digital I/Os, 6 grounds, and 10 pins that are connected to pads adjacent to the breadboard area. The pin-out for the connector is shown in Table 3-4 with the FPGA pin which corresponds with the connector pin. The mating connector is made by Samtec. The recommended cable is part number FFSD-20D-1201-N (12 inches long). See section on Digital Buffers for more detail.

Table 3-4. Digital I/O Pin Description

* Use 210 for clock input.

3.10.4 Analog I/O Connectors

One analog I/O connector is a 20-pin, 50 mil, double-rowconnector designated J16; Figure 3-2 shows how this connector is positioned and oriented on the board. The odd number pins go to the a wiring and a 0603 pad which allows a jumper to connect these pins to the breadboard area.. The even number pins have a position for a ground jumper and/or a hole for wiring. This facilitates single-ended inputs by using the jumper and allows differential inputs by omitting the jumper and using a wire. The pin-out for the connector is shown in Table 3-5; no connections are permanently make to this connector although jumpers can be used to connect the pins as described above. The mating connector is made by Samtec. The recommended cable is part number FFSD-25D-1201-N (12 inches long).

Positions for four SMB coaxial connectors are in the analog connector area of the board designated J3, J4, J5, and J6. Figure 3-2 shows how the four right angle connectors are normally positioned and oriented on the board. However, these connectors may be placed in several alternate positions. All four connectors may be placed on the top of the board. Connectors J5 and J6 must be faced a different direction from the way shown in Figure 3-2 usually facing opposite directions along the long dimension of the board. All four connectors may be placed on the bottom side of the board as well with any combination of straight or right angle connectors. If clearance is not restricted by other daughterboards, using four straight connectors in the most convenient for connecting and disconnecting.

Both terminals of these connectors have connections to the amplifier and transformer area by using jumper pads next to the connectors. The shell may also be connected to ground with a jumper.

Table 3-5. Analog I/O Pin Description (AED-300)

3.11 Internal Interfaces

3.11.1 Mixed Signal Area to FPGA Connections

Table 3-6 gives the interconnection between the mixed signal area and the FPGA.

Table 3-6. Mixed Signal Area Interconnection to FPGA

1. TMS320C601/6701 Evaluation Module Technical Reference, (literature number SPRU305), Texas Instruments, 1998.