The Signalware AED-300 daughterboard is designed to provide the user with maximum configuration flexibility. Beside the breadboard area and mixed signal mounting area described below, there are several components which are user selectable. These components select the bias voltage to the mixed signal mounting area, provide grounding on the analog signal connector and pull-up resistors on logic inputs. They are 0603 size, surface-mount parts to minimize area required.
The mixed signal mounting area is designed to make mounting of A/D and D/A converters very easy. It can handle both serial and parallel digital interface converters which are surface mount and have .64 or .65 mm pin spacing. The mounting area has two rows of 84 pin pads that could accommodate several chips mounted end to end with as many as 84 total pins. Each pair of pads (one in each row) is called a position. For example, 6 - 28 pin devices which occupy 14 positions each could be mounted using all 84 positions (6x14 = 84), or 8 - 20 pin devices which occupy 10 positions each could be mounted with 4 positions left unused (8x10 = 80).
Figure 2-1 shows the two rows of pads where devices are mounted marked
analog and digital pin pads. These pads divide the mixed signal mounting
area into an analog and digital side. The analog and digital components
are mounted in the respective component areas and on the reverse side of
the board under the respective sides of the area.
The digital component area contains provision to connect each pin to digital ground, to an FPGA pin, to a wire and/or to one of two buses called the D_3.3V bus and the Y-bus. The Y-bus may be connected to D_5.0V or wired to any signal used in several places on the digital side.
The analog component area contains provision to connect each pin to analog ground, to a wire and/or to one of 4 buses called A_5.0V, Ref1, Ref2, and analog ground. The Ref1 and Ref2 buses may be connected to 1.024V, 2.048V, 4.096V, the output of a regulator for low voltage analog power, or any signals used in several places on the analog side . See Reference Supplies below.
All of the connections listed above may be done with an 0603 size passive component. This includes resistors, capacitors, inductors and jumpers (0.0 ohm resistors). Thus single pole filters for signal pin and power supply pins may be created. On the analog side, connection to the Ref2 and the analog ground bus are separated from the pin by a series passive component and an additional wireing hole allowing circuits with 3 or 4 components to be constructed.
2.1.2 Amplifiers
The Signalware AED-300 daughterboard supports two dual operational amplifiers and two single operational amplifiers. The user may mount a wide variety of amplifiers in these positions. For the dual amplifier Texas Instruments THS4002, THS4032, THS4052 or THS4062 are suggested. For the single amplifier Texas Instruments THS3001, THS4001, THS4031, THS4051 or THS4061 are suggested.. A large variety of amplifier circuits is possible with the board layout surrounding these amplifiers including active filters. See Daughterboard Descriptions for more details.
Also four transformers may be mounted in this area to provide interface for mixed signal devices. The Mini Circuits KK81 series devices are suggested.
The Signalware AED-300 daughterboard breadboard also provides mounting for SOIC and wide SOIC surface mount package devices and DIP through-hole components. In this area, amplifiers and filters can be conveniently placed to perform analog signal conditioning for both A/D and D/A converters.
FPGA configurations are used to configure the digital logic in the FPGA to interface between the devices mounted in the mixed signal area and the DSP's parallel EMIF bus or the serial McBSP ports. The AED-300 is initially configured with a test configuration that tests the interface between the FPGA and the DSP.
Tools for developing and downloading FPGA configurations are available from Xilinx. The ISE Series PC based development tools include a free, very basic version (Web Pack), standard user version (BASE X), and full capability versions. The basic version will configure the AED-300 with selected Virtex E FPGA options. The BASE X version add the capability of generating new library parts. See the Xilinx web site for more detail. The iMPACT tool, available free on the Xilinx web site, provides for downloading all FPGA devices used on the AED300 board; however, a JTAG FPGA cable is required.
There are two methods that can be used to configure the Xilinx Spartan XL series or the Virtex E FPGA with its logic configuration on the AED-300 daughterboard: 1) use of the serial PROM or flash configuration memory; 2) the use of the Xilinx iMPACT tool in the boundary scan mode (JTAG).
1) The nominal method of configuration on the AED-300 board is via the serial configuration memory. For this method, the FPGA must be set to the Master Serial mode with all I/O pins pulled up prior to completion of configuration. This is accomplished with resistors (R1, R2, and R3) that pull down the appropriate mode pins on the FPGA. (For the Spartan XL series, a 4.7k Ohm resistor on R2 is used to pull down only the M0 mode pin; for Virtex E, only M0 and M1 are pulled down with 0.0 Ohm resistors on R2 and R3 while M2 remains high with an internal pull-up.) In this mode, the FPGA is automatically configured from the serial configuration memory on power-up.
Either serial PROM (default) or flash configuration memory may be supplied with the board. All optional Virtex E FPGAs are supplied with flash as follows:
For boards with serial PROM, the making of a serial PROM is described is in a separate section below; the PROM is then inserted in the daughterboard prior to power up. For boards with flash configuration memory, the flash memory may be programmed on the board with the Xilinx iMPACT tool. The flash configuration memory is in the JTAG chain with the FPGA. The board will have either or both of the flash configuration memory devices (U9 or U10) depending of the FPGA mounted on the board.
2) The Xilinx Programmer, iMPACT (supplied with Xilinx tools), is the preferred method for configuring the FPGA with its program while debugging. The flash and the FPGA (in that order) must be configured in a chain during the setup of iMPACT. The appropriate configuration files must be selected for each device. FPGA devices use ".bit" files, and the flash devices use ".mcs" files. The ".mcs" file is made from the ".bit" file using Xilinx's Prom File Formatter. iMPACT uses the download cable (supplied by Xilinx or Insight) and the JTAG connector (J1) on the AED-101 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low while using iMPACT to program the FPGA.
When using iMPACT to program a flash device, the jumper across pins 1 and 2 of J1 can be removed. When the board is powered up with a jumper across pins 1 and 2 of J1, the FPGA will not be loaded from the configuration memory. It will sit un-configured until loaded from iMPACT, or until the jumper is removed (LED1 will light when the FPGA is not configured). The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground are also connected to the Xilinx download cable. After powering up the daughterboard, the FPGA or flash is ready to program.
When using iMPACT, it is not necessary to program both the FPGA and the flash. Load the program into the FPGA when you only want that program to exist while the power is on. When you shut the power off, the FPGA will lose its program. If you want the FPGA to be loaded with the same program the next time you turn the power on, you should load the program into the flash instead of the FPGA. The FPGA will continue to be loaded with that same program until you reprogram the flash. Refer to the section on JTAG Port for FPGA Programming for the pin-out of J1.
Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with an XCS20XL FPGA use an XC17S20XL serial PROM, an XCS30XL FPGA uses an XC17S30XL serial PROM, and an XCS40XL FPGA uses an XCS40XL serial PROM. Daughterboards with an XCV50E or XCV100E FPGA use an XC1701L serial PROM.
After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.
The test configuration provides a test of the parallel EMIF interface between the DSP and the FPGA and the 16 digital I/O lines. It does not provide for use of the 56 connections to the mixed signal area. The user must provide the custom configuration for the devices that are to be mounted in the mixed signal area. (For Signalware 3xx boards where devices have been mounted by Signalware in the mixed signal area, Signalware provides a FPGA configuration that operates these connections as necessary for the devices mounted.)
In order to make the test program as flexible as possible, several control registers are provided inside the FPGA. All the registers are memory mapped and 16 bits wide. However, in 32-bit word DSP target boards with byte addressing, they are given addresses as if they were 32 bits (or 4 bytes) wide with zero for bits 0 and 1. In 16 bit word DSP target boards, these address are shifted right by two bits. In Table 2-3, both addresses are shown. Although the high order bits are shown as zero, they may have to be set to some value to address the daughterboard that depends on the DSP target board that is used. The address bits that are not connected to the FPGA (bits 13 to 6 of byte address or bits 11 to 4 of word address) are also shown as zero, but they are "don't care". The table also gives the "testing value" which is the value that the example DSP program loads into the registers for 100 MHz daughterboard clock with 256 sample frame length. The testing values give maximum performance that the target board provides. By default, the daughterboard clock equals the target board CLKOUT2 clock.
The test data word sent from the FPGA to the DSP is composed of two 16 bit fields. The first field, bits 0-15, is the interrupt clock counter incrementing at the CLKOUT2 rate. The second field, bits 16-31, is a counter value that increments each time the DSP reads a data word.
Table 2-1. FPGA Control Registers
| Register Name | Byte Addressing | 16-bit Word Addressing | Read/Write Capability | Testing Value |
| Digital I/O | 0x00100000 | 0x040000 | R/W | 0x0001 |
| Digital I/O Control | 0x00100004 | 0x040001 | R/W | 0x3000 |
| Interrupt Start | 0x00120004 | 0x048001 | R/W | 0x0100 |
| Interrupt Period | 0x00120008 | 0x048002 | R/W | 0x0100 |
| Interrupt Down Counter | 0x0012000C | 0x048003 | Read Only | N/A |
The formats for the Digital I/O registers are provided in Appendix D. Interrupt Start and Interrupt Period registers are 16 bit counts of board clock from start up to first interrupt and from one interrupt to the next. The interrupt counting is visible in the Interrupt Down Counter register.
The AED-300 daughterboard mounts to the EVM's expansion connectors with the breadboard area closest to the back panel. It is crucial that the standoffs provided be used when mounting the daughterboard to the EVM board. These provide a mating height of 11.9 mm. Using anything smaller than 12.0 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the EVM board, it should be secured with four M3 x .5 x 6mm screws through the mounting holes provided on the EVM board.
If the EVM board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off install the EVM and daughtercard.
Upon powering up the EVM board, the FPGA sample program is automatically loaded and running. To test the daughterboard, examine the results of running the DSP test program. This program, "dddddd_aed300.out" where dddddd is the development board identifier, can be found on the floppy disk provided with the board. Before loading the program with the 6x01 EVM development boards, reset the EVM board with the reset utility. If the utility is used with speed option 3, the EVM clock speed to the higher frequency CPU speed available on that board. Now load and run the program using Code Composer Studio. The format of the output is described in Figures 2-1 and 2-2.
Referring to Figure 2-2, before the OK is printed at the end of the window, the DSP program operates all of the digital I/O on J15. During the printing before the "Checking the Digital Outputs ....", all digital I/O lines are disabled (high-Z). Then each of the 24 digital I/O lines is turned on one at a time for about 1 second. Finally, the OK is printed.
Referring to Figure 2-3, the words that are received from the FPGA consist of two 16 bit fields which are printed in two of the "www" fields as a sample from one record of the incoming data and averaged in the "uuu" fields for the ten records received. In each word, the lower 16 bits (0-15) are the I/O bus clock counter in the FPGA (80 MHz in the C6x01, high speed); the upper 16 bits (16-31) are a sequential count of the words transmitted from the FPGA. The lower 16 bits (fast counter) are printed in the first "www" field (column) and first "uuu" (row) field, and the upper 16 bits (sequential counter) are printed in the second "www" and "uuu" fields.
Figure 2-2. Display Window for AED-300 Test Program
Line| Display Window
No. | Content
----+------------------------------------------------------------
001 |*** AED 300 TEST PROGRAM STARTED ***
002 |Begin application processing (Block size = zz)
003 |Interrupts received = yy
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |C= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
015 |D= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
016 |E= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
017 |F= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
018 |G= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
019 |H= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
020 |I= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
021 |J= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
022 |K= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
023 |L= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
024 |M= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
025 |N= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
026 |O= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
027 |P= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
028 |[dd] www www www www www www www www www www www www www www www www
029 |[dd] www www www www www www www www www www www www www www www www
030 |[dd] www www www www www www www www www www www www www www www www
031 |[dd] www www www www www www www www www www www www www www www www
032 |[dd] www www www www www www www www www www www www www www www www
033 |[dd] www www www www www www www www www www www www www www www www
034 |[dd] www www www www www www www www www www www www www www www www
035 |[dd] www www www www www www www www www www www www www www www www
036 |[dd] www www www www www www www www www www www www www www www www
037 |[dd] www www www www www www www www www www www www www www www www
038 |[dd] www www www www www www www www www www www www www www www www
039 |[dd] www www www www www www www www www www www www www www www www
040 |[dd] www www www www www www www www www www www www www www www www
041 |[dd] www www www www www www www www www www www www www www www www
042 |[dd] www www www www www www www www www www www www www www www www
043 |[dd] www www www www www www www www www www www www www www www www
044 |Checking Digital Outputs ....
045 |OK
Figure 2-3. Description of Display Window Content
Line |R/O| Explanation of Line Nos.
| | Content
---------+---+----------------------------------------------------------
001 | R |Indicates EVM board is communicating with host
002 | R |Ready to start DMA and application processing
| | zz = buffer size in bytes
003 | R |Indicates if data is received from daughterboard
| | yy = number of frame interrupts received
004 | O |A "read drop error" occured in DMA processing
| | ee = error code (1 = RDROP bit set;
| | -1 = neither RDROP or Frame Complete set)
| | pp = number of buffer last processed
| | cc = DMA transfer count
005 | O |Application program requested termination
| | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
| R | ll = number of times buffer ready tested
| | mm = number of buffers processed by application
| | rr = number of buffers recieved from DMA
008-011 | R |Address and block number of each block processed
| | aaaa = hexidecimal value of buffer address
| | bb = number of the block as received from DMA
012-027 | R |Averages of values from A/D in the columns of each block.
| | The records contain 16 columns. The averages for the
| | columns are in separate lines labeled A through P.
| | uuu = unsigned average value for the block
028-043 | R |Samples (256) from the first buffer of data processed
| | dd = index of first word in row
| | www = hexidecimal value of word
044 | R |Checking digital I/O is in process
045 | R |Processing is terminated
R = required in display window, O = optional in display window