The AED-300 daughterboard is designed to facilitate construction of prototypes or quickly make small production runs for various analog and digital interfaces with Texas Instruments Digital Signal Processors. It fits the expansion slot of Texas Instruments Digital Signal Processing Evaluation Modules (EVM) and DSP Starter Kits (DSK) for TMS320C6xxx and C5xxx DSPs made by Texas Instruments, DNA Enterprises, Inc., and Spectrum Digital. This expansion slot has both an expansion memory interface and an expansion peripheral interface which allows the daughterboard full access to all of the DSP's resources.
The AED-300 has a wide variety of applications that require digital interface to mixed signal devices with clock rates as high as about 100 MHz. Mixed signal devices include A/D converters, D/A converters, comparitors, line drivers (RS422, RS485, RS232, TTL, LVTTL, low voltage differential, etc.), and other devices that have both a digital interface and analog signal pins. All digital devices may be mounted also. These devices are mounted in the mixed signal area.
Figure 1-1 shows the organization of the AED-300 daughterboard. Beside
the mixed signal area, the board contains amplifier and bread board areas
and areas for 16 LVTTL digital I/O lines, flash memory devices, FPGA,
interfaces to the DSP memory bus and peripherals and analog connectors.
The board also provides for mounting of additional analog components in three areas: 1) 2 dual amplifiers may be mounted in an area specially designed to provide a variety of circuits to use the amplifiers to convert single-ended inputs to differential, filter input signals and/or buffer two separate signals. 2) 2 single amplifiers mounted in an area specifically for filtering and buffering output signals. 3) And, a bread board area designed to mount surface-mount (SOIC) and DIP analog components.
In the mixed signal mounting area between 4 and 20 surface-mount SSOP or TSOP packaged devices can be mounted. All devices with packages that have a pin spacing of .64 or .65 mm, pins on only two sides of the device, and an overall width between 3 mm and 9 mm can be mounted in the mixed signal area. The devices are placed in a row of 84 pin spaces, end-to-end, so that one side faces the FPGA for digital connection and the other faces the amplifier for analog connection. On the side for digital connections, the choices include the FPGA, digital ground, +3.3V digital, and a general purpose bus. On the side for analog connections, the choices are +5V analog, analog ground, and two general purpose buses with selectable bias voltage and low voltage analog.
The breadboard area consists of 3 sq. in. of 50 mil pitch surface-mount SOIC or DIP (.3 or .6 inch) component area. This allows a wide variety of components to be wired into signal conditioning circuits. The breadboard area is served by separate + and - regulated power supplies for sensitive analog components. For connecting analog signals, four SMB coax connectors and a 20 pin, 25 mil ribbon cable connector are adjacent to the breadboard at the edge of the daughterboard where ribbon cable and coax connectors are easily attached.
The advantage of this daughterboard over boards that contain only the A/D converters is that it provides for analog signal conditioning circuits and for digital preprocessing before the sampled data is placed in the DSP memory. Similarly for D/A converters, digital post processing of the output data samples can be included between the DSP and the converter; and analog signal conditioning can follow the converter. This allows prototypes with the complete front end design which is often essential to successful development in complex applications of the DSP. The inputs to the A/D converters and the outputs of the D/A converters lead directly to a breadboard area on which conditioning circuits can be constructed. The A/D and D/A converters have their digital interfaces connected directly to a Xilinx FPGA which provides a flexible digital interface to the DSP.
The strategic location of the FPGA between the DSP and the converters allows it to perform many useful functions. It allows blocking and FIFO buffering of signals before they are placed in the DSP memory. This can optimize the use of DSP memory and memory bus bandwidth which is often a limiting factor in DSP applications. The FPGA can provide an input decimation filter which limits the bandwidth with sharp digital filter edges and reduces the number of samples allowing the application to work with higher initial sample rates than the DSP can handle. The FPGA can construct high speed output samples for the D/A converters based on DSP inputs or the signal coming from the A/D converters. The FPGA also connects to the external digital I/O connector and to the clock/control lines of the converters. This allows synchronization of the converters with both external signals and with DSP signals.
SIGNALWARE provides technical support for all aspects of the use of the AED-300 including signal conditioning circuit design, FPGA configuration programming, and DSP software programming. SIGNALWARE can provide a turnkey solution to prototyping a DSP application. Signal conditioning circuits can be mounted and wired on the board at the time of manufacture at less cost than having a technician or engineer wire them on the board afterward. SIGNALWARE also provides a 90 day limited warranty against workmanship and component defects.