The Signalware AED-200 daughterboard is designed to provide the user with maximum configuration flexibility. Besides the breadboard area and mixed signal mounting area described below, there are several components which are user selectable. These components select the bias voltage to the mixed signal mounting area, provide grounding on the analog signal connector and pull-up resistors on logic inputs. They are 0603 size, surface-mount parts to minimize area required.
The mixed signal mounting area is designed to make mounting of A/D and D/A converters very easy. It can handle both serial and parallel digital interface converters which are surface mount and have 50 mil pin spacing in the SOIC or wide SOIC package. The mounting area has two rows of 42 pin pads that could accommodate several chips mounted end to end with as many as 84 total pins. For example 3 - 28 pin devices could be mounted, or 4 - 20 pin devices could be mounted with 2 positions left unused.
Each pair of pads (one in each row) is called a position. AED-200 ADC Mounting Table gives the numbers of positions required for various A/D converters. AED-200 DAC Mounting Table gives the numbers of positons required for various D/A converters.
The reference voltage used for A/D and D/A may be selected by R90. See Reference Supplies below.
The Signalware AED-200 daughterboard breadboard also provides mounting for SOIC and wide SOIC package devices and DIP through-hole components. In this area, amplifiers and filters can be conveniently placed to perform analog signal conditioning for both A/D and D/A converters.
Tools for developing and downloading FPGA programs are available from Xilinx. The Foundation Series Software tools (not ISE tools) offers both a low cost introductory version (basic) and a full capability version. The basic version will program the standard board and some limited number of FPGA options. FPGA programs are used to configure the FPGA to perform its customized function.
There are three methods that can be used to configure the Xilinx Spartan XL series or the Virtex FPGA with its program on the AED-200 daughterboard: 1) use of the serial PROM or flash configuration memory, 2) the JTAG Programmer, or 3) the Hardware Debugger.
1) The nominal method of configuration on the AED-200 board is via the serial configuration memory. For this method, the FPGA must be set to the Master Serial mode with all I/O pins pulled up prior to completion of configuration. This is accomplished with resistors (R1, R2, and R3) that pull down the appropriate mode pins on the FPGA. (For the Spartan XL series, 4.7k Ohm resistor is used on R2 for only one mode pin; for Virtex, only M0 and M1 are pulled down with 0.0 Ohm resistors on R2 and R3 while M2 remains high with an internal pull-up.) In this mode, the FPGA is automatically configured from the serial configuration memory on power-up. This method is good for a final program, but is not convenient when debugging programs.
Either serial PROM or flash configuration memory may be supplied with the board. For boards with serial PROM, the making of a serial PROM is described is in a separate section below; the PROM is then inserted in the daughterboard prior to power up. For boards with flash configuration memory, the flash memory may be programmed on the board with the JTAG Programmer. The flash configuration memory is in the JTAG chain with the FPGA. The board will have either or both of the flash configuration memory devices (U9 or U10) depending of the FPGA mounted on the board.
2) The JTAG Programmer (supplied with Xilinx tools) is the preferred method for configuring the FPGA with its program while debugging. If the daughterboard has flash configuration memory, the JTAG Programmer can also download the FPGA program to flash configuration memory. The flash and the FPGA (in that order) must be configured in a chain in the setup of the JTAG Programmer. The appropriate configuration files must be selected for each device. The JTAG Programmer uses the download cable (also supplied by Xilinx) and the JTAG connector (J1) on the AED-200 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low while using the JTAG Programmer. The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground are also connected to the Xilinx download cable, and the FPGA or flash is ready to program. Refer to the section on JTAG Port for FPGA Programming for the pin-out of J1.
3) The Hardware Debugger (also supplied with Xilinx tools) is a second method for downloading programs to the FPGA while debugging. The pins CCLK, DONE, DIN, PROG, power, and ground on J1 are used with the Hardware Debugger. INIT should not be pulled low as it is when using the JTAG Programmer. The FPGA must be in the Slave Serial mode with I/O pins pulled up prior to completion of configuration. (For the Spartan XL series, the mode pins are internally pulled high by removing R2; for Virtex, only M2 is pulled down with a 0.0 Ohm resistors on R1 while M0 and M2 remain high with internal pull-up resistors.)
Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with an XCS20XL FPGA use an XC17S20XL serial PROM, an XCS30XL FPGA uses an XC17S30XL serial PROM, and an XCS40XL FPGA uses an XCS40XL serial PROM. Daughterboards with an XCV50, XCV100, or XCV150 FPGA use an XC1701L serial PROM.
After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.
The AED-200 daughterboard mounts to the EVM's expansion connectors with the breadboard area closest to the back panel. It is crucial that the standoffs provided be used when mounting the daughterboard to the EVM board. These provide a mating height of 11.9 mm. Using anything smaller than 12.0 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the EVM board, it should be secured with four M3 x .5 x 6mm screws through the mounting holes provided on the EVM board.
If the EVM board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off install the EVM and daughtercard.
Upon powering up the EVM board, the FPGA sample program is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "aed200.out", can be found on the provided floppy disk. Before loading the program, reset the EVM board with the speed option set to 3. This sets the EVM clock speed to 160 MHz. Now load and run the program using Code Composer Studio. The format of the output is described in Figures 2-1 and 2-2.
Referring to Figure 2-1, before the OK is printed at the end of the window, the DSP program operates all of the digital I/O on J15. During the printing before the OK, all digital I/O lines are disabled (high-Z). Then each of the 24 digital I/O lines is turned on one at a time for about 1 second. Finally, the OK is printed.
Referring to Figure 2-2, the words that are received from the FPGA consist of two 16 bit fields which are printed in two of the "www" fields as a sample from one record of the incoming data and averaged in the "uuu" fields for the ten records received. In each word, the lower 16 bits (0-15) are the I/O bus clock counter in the FPGA (80 MHz in the C6x01, high speed); the upper 16 bits (16-31) are a sequential count of the words transmitted from the FPGA. The lower 16 bits (fast counter) are printed in the first "www" field (column) and first "uuu" (row) field, and the upper 16 bits (sequential counter) are printed in the second "www" and "uuu" fields.
Figure 2-1. Display Window for AED-200 Test Program
Line| Display Window
No. | Content
----+------------------------------------------------------------
001 |*** AED TEST PROGRAM STARTED
***
002 |Buffer Allocation Error [ssXyy]
003 |Begin application processing (Buffer size = zz)
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |C= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
015 |D= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
016 |E= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
017 |F= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
018 |G= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
019 |H= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
020 |I= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
021 |J= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
022 |K= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
023 |L= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
024 |M= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
025 |N= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
026 |O= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
027 |P= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
028 |[dd] www www www www www www www www www www www www www www www
www
029 |[dd] www www www www www www www www www www www www www www www
www
030 |[dd] www www www www www www www www www www www www www www www
www
031 |[dd] www www www www www www www www www www www www www www www
www
032 |[dd] www www www www www www www www www www www www www www www
www
033 |[dd] www www www www www www www www www www www www www www www
www
034 |[dd] www www www www www www www www www www www www www www www
www
035 |[dd] www www www www www www www www www www www www www www www
www
036 |[dd] www www www www www www www www www www www www www www www
www
037 |[dd] www www www www www www www www www www www www www www www
www
038 |[dd] www www www www www www www www www www www www www www www
www
039 |[dd] www www www www www www www www www www www www www www www
www
040 |[dd] www www www www www www www www www www www www www www www
www
041 |[dd] www www www www www www www www www www www www www www www
www
042 |[dd] www www www www www www www www www www www www www www www
www
043 |[dd] www www www www www www www www www www www www www www www
www
044 |OK
Figure 2-2. Description of Display Window Content
Line|R/O| Explanation of Line
Nos.| - | Content
----+---+--------------------------------------------------------------
001 | R |Indicates EVM board is
communicating
002 | O |Buffers could not be allocated in heap (teminates program)
002 | O | ss = size of each buffer in bytes
002 | O | yy = number of buffers required
003 | R |Ready to start DMA and application processing
003 | R | zz = buffer size in bytes
004 | O |A "read drop error" occured in DMA processing
004 | O | ee = error code (1 = RDROP bit set;
004 | O | -1 = neither RDROP or Frame Complete set)
004 | O | pp = number of buffer last processed
004 | O | cc = DMA transfer count
005 | O |Application program requested termination
005 | O | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | R | mm = number of buffers processed by application
007 | R | rr = number of buffers recieved from DMA
008 | R |Address and block number of each block processed
-011| R |
008 | R | aaaa = hexidecimal value of buffer address
008 | R | bb = number of the block as received from DMA
012 | R |Averages of values from A/D in the columns of each block.
The
-027| R |
012 | R | records contain 16 columns. The averages for the columns
are in
012 | R | separate lines labeled A through P.
012 | R | uuu = unsigned average value for the block
028 | R |Samples (256) from the first buffer of data processed
-043| R |
028 | R | dd = index of first word in row
028 | R | www = hexidecimal value of word
044 | R |Processing is terminated
R = required in display window, O = optional in display window