5. TROUBLESHOOTING

5.1 Symptoms & Solutions

The following is a list of symptoms for problems encountered prior to the last update of this manual. This list is maintained on the SIGNALWARE web site. Refer to it for the most recent list of symptoms.

5.1.1 Problems with Example Program

The following symptoms and solutions assume that the SPROM supplied for the example program is correctly seated in its socket and that no additions or modifications have been made to the board.

Symptom: The EVM/DSK will not reset.

Diagnosis: Remove the daughterboard and run reset.

Result 1: The EVM/DSK will reset successfully without the daughterboard:

Solution 1: Contact SIGNALWARE warranty support.

Result 2: The EVM/DSK will not reset without the daughterboard:

Solution 2: EVM/DSK installation is not completed correctly. Un-install the board support software with Add/Remove Program, power down and remove the EVM board, and reboot. Remove the EVMxxx.inf and .vxd modules from the windows directories, install the board software, and power down. Install the EVM board and reboot. If this fails to correct the problem, see the EVM board manual and/or contact Texas Instruments or the board manufacturer. Note: Board support versions prior to Code Composer Studio do not work on Windows 98.

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Symptom: The EVM/DSK will not pass confidence test, but it does reset.

Diagnosis: Remove the daughterboard and run confidence test.

Result 1: The EVM/DSK will run confidence test successfully without the daughterboard:

Solution 1: Contact SIGNALWARE warranty support.

Result 2: The EVM/DSK will not run confidence test without the daughterboard:

Solution 2: The board hardware is not working correctly. Contact Texas Instruments or the board manufacturer.

Symptom: The SIGNALWARE example program issues no messages after start up, but the EVM/DSK passes confidence test.

Solution: The program did not load and start correctly. Close Code Composer Studio (or debugger if using version 1.x tool set), reset the EVM/DSK, restart Code Composer, reload the example program. If that does not correct the problem, run example programs supplied by the EVM/DSK manufacturer to ensure proper operation of the DSP. Contact Texas Instruments or the board manufacturer if the example programs do not run correctly from Code Composer. Check the readme file on the SIGNALWARE distribution floppy disk for the restrictions on the program operation. Otherwise, contact SIGNALWARE warranty support.

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Symptom: The SIGNALWARE example program issues "Start data transfer" message and continues to run without producing more output.

Diagnosis: Run the "without board" version of the SIGNALWARE example program.

Result 1: The "without board" version of the example program does NOT run correctly.

Solution 1: SIGNALWARE example program is not compatible with the EVM/DSK. Check the readme file on the SIGNALWARE distribution floppy disk for the restrictions on the program operation. Otherwise, contact SIGNALWARE warranty support.

Result 2: The "without board" version of the example program does run correctly.

Solution 2: The DSP is not receiving interrupts from the daughterboard. Check that the daughter board is seated correctly and that the SPROM supplied for the SIGNALWARE example program is in the socket correctly. See FPGA Problems with SPROM Configuration below.

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5.1.2 FPGA Problems with JTAG Configuration

Symptom: The FPGA does not appear to be operating.

Diagnosis: Check the DONE pin on the FPGA.

Result 1: The DONE pin is NOT high (above 2.4 VDC).

Solution 1: The FPGA has failed to configure correctly. Check that the INIT pin is pulled low. Check that the wires to the programming connector are correct and solidly connected. Check that the configuration file has been generated for the correct FPGA. For example, a file generated for a XC4010XL will not configure a XC4044XL. Otherwise, contact FPGA manufacturer for configuration failure diagnosis procedure.

Result 2: The DONE pin is high (above 2.4 VDC).

Solution 2: The FPGA completed the configuration procedure; see FPGA Problems after Completing Configuration.

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5.1.3 FPGA Problems with SPROM Configuration

Symptom: The FPGA does not appear to be operating.

Diagnosis: Check the DONE pin on the FPGA.

Result 1: The DONE pin is NOT high (above 2.4 VDC).

Solution 1: The FPGA has failed to configure correctly. Check the SPROM socket to insure that pins are not bent and that the SPROM is seated correctly. Check that the SPROM will verify against the configuration file. Check that the SPROM option has been set to "Active Low". Check that the configuration file has been generated for the correct FPGA. For example, a file generated for a XC4010XL will not configure a XC4044XL. Check that the mode pins on the FPGA are set properly, i.e. master-serial mode (see section on Configuration Modes). Otherwise, contact FPGA manufacturer for configuration failure diagnosis procedure.

Result 2: The DONE pin is high (above 2.4 VDC).

Solution 2: The FPGA completed the configuration procedure; if the SIGNALWARE example program runs correctly, see FPGA Problems after Completing Configuration. Otherwise contact SIGNALWARE warranty support.

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5.1.4 FPGA Problems with Hardware Debugger Configuration

Symptom: The FPGA Hardware Debugger says the DONE pin did not go high.

Solution: The FPGA has failed to configure correctly. Check that the wires to the programming connector are correct and solidly connected. Check that the FPGA is in the correct programming mode, i.e. slave-serial (see section on Configuration Modes). Check that the configuration file has been generated for the correct FPGA. For example, a file generated for a XC4010XL will not configure a XC4044XL. Otherwise, contact the FPGA manufacturer for configuration failure diagnosis procedure.

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5.1.5 FPGA Problems after Completing Configuration

Symptom: The FPGA does not appear to operate after completing configuration, but the example program does operate.

Diagnosis: Add a test output to the configuration which counts down the XCLKOUT2 input to the FPGA by 2 or more so that signal can be seen on your test instrument (logic analyzer, oscilloscope or voltmeter can be used for the test). Use a spare pin on the FPGA (possibly one on the logic analyzer connector) or use a buffered digital output pin.

Result 1: The test output does NOT have the divided clock signal.

Solution 1: The FPGA has failed or is not getting the clock input. Check the clock signal on the input pin to the FPGA. If there is no clock signal, contact SIGNALWARE warranty support. Otherwise, contact the FPGA manufacturer and open a case with the symptoms and configuration you are using.

Result 2: The test output does have the divided clock signal.

Solution 2: The configuration is not working as intended. Perform a timing simulation on the configuration which matches exactly the inputs observed on the FPGA pins. Check carefully for setup and hold time problems on the devices in the FPGA. Check all the output pins for match to the signals shown in the timing simulation. Adding additional test pins with critical internal signals can help diagnose the problem. Otherwise, contact FPGA manufacturer and open a case with the symptoms and configuration you are using. SIGNALWARE technical support services are available to assist in diagnosis of FPGA configuration design problems.

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Symptom: Some FPGA output pins operate correctly, but some do not.

Diagnosis: Add a test output to the configuration which duplicates the incorrect output on a pin that seems to operate correctly. Use a spare pin on the FPGA (possibly one on the logic analyzer connector) or use a buffered digital output pin.

Result 1: The test output matches the incorrect output signal.

Solution 1: The FPGA configuration programmed does not have the desired effect. If a timing simulation shows a correct signal, the problem is either that the simulation does not have an accurate copy of the input signals or has a setup or hold problem which as not been detected by the tools. Otherwise, contact the FPGA manufacturer and open a case with the symptoms and configuration you are using. SIGNALWARE technical support services are available to assist in diagnosis of FPGA configuration design problems.

Result 2: The test output is correct (matching timing simulation), and does not match the incorrect output signal.

Solution 2: If the incorrect signal pin is used to drive a digital output buffer, verify that the direction pin on the buffer device is set so that buffer is not driving the incorrect output pin. With the daughterboard disconnected from the EVM, verify with ohmmeter that the incorrect signal pin is not shorted to any other FPGA pin, ground, or supply voltage, and that it connects to other points as shown in the schematic. If there is a short, contact SIGNALWARE warranty service. Otherwise, contact the FPGA manufacturer and open a case with the symptoms and configuration you are using.

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5.1.6 Problems after Additions or Modifications to Daughterboard

After making additions or modifications to the daughterboard, it is essential that all 8 or 9 power buses on the daughterboard be checked for shorts before the daughterboard is mounted on the EVM/DSK boards. An ohmmeter check before and after the change can pick up most wiring errors. If polarized capacitors have been added or replaced, the polarity must be checked separately by inspection as the ohmmeter check may not pick up a reversed polarized capacitor. Shorts or reversed capacitors on the daughterboard power buses can result in damage to the EVM/DSK board, to the daughterboard and to a PC host. Neither the PC host nor the EVM/DSK boards have sufficient current limiting to prevent damage to traces or components on the EVM/DSK or daughterboard.

The buses to be checked include some or all of those shown in Table 5-1.

If these buses appear to be free of shorts, the daughterboard can be connected to the EVM/DSK and placed in the PC. When the PC is powered up, immediately look for any indications of overload indications and turn power off immediately if any overload indication is observed. Overload indications may include any (usually green) power LED on the EVM/DSK not immediately lighting, unusual peeps from the PC, monitor not displaying appropriate BIOS lines, unusual odors, or any visual indication of heat. Immediately begin checking all buses listed above for incorrect voltage. Begin with the Analog +/- regulated buses and work up the list. Test points are available on the back of the daughterboard for these buses except some daughter boards do not have +/- 12 volt test points. Turn off power immediately if any incorrect voltage is observed.

Symptom: A power supply bus has an incorrect voltage.

Solution: The bus may have a (partial) short, the bus which supplies that bus may have a (partial) short, or added circuit design may have overloaded the bus. Check that the current limitations are not being exceeded on that bus by the new circuitry. Remove connections to that bus from the new circuitry until the symptom is corrected. If the bus does not regain its correct voltage, contact SIGNALWARE repair service. Check the remaining buses for correct voltage. Repeat the example program tests to determine if any damage has resulted from the overload. Contact SIGNALWARE repair service if any problem is encountered; ship both EVM/DSK and daughterboard to SIGNALWARE for repair.

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5.2 Test Points

The daughterboard has several test points which are labeled on the bottom side of the board so that they can be read with the board mounted on the EVM. The holes of the test points are of such a size that temporary test points can be inserted such as the PC Test Points made by Keystone (Red #5005; Black #5006; White #5007) available from Digi-Key. Table 5-2 shows the test points for each daughterboard.