3. DAUGHTERBOARD DESCRIPTION

3.1 Block Diagram

The block diagram in Figure 3-1 shows the major hardware components including optional flash with a hypothetical FPGA program that demonstrates the use of all these components.

Figure 3-1. AED-103 Block Diagram

The following subsections reference to this block diagram and the schematics in Appendix A.

3.2 FPGA Functions

The FPGA is referenced as U1 on the daughterboard and uses a PQ or HQ 240 package. All of the signals in the EVM external interfaces feed into the FPGA. The FPGA is also connected to the control lines on the flash, and all of the digital lines of the converters. Alternately, the smaller interior footprint referenced as U3 can be used for smaller, optional FPGAs with a PQ/HQ 208 package.

The 16 digital I/O are not shown in Figure 3-1. These connect from the FPGA to a 74LVTH244 buffer (U20) and a 74LVTH245 transceiver (U19), and then to a 40-pin connector (J15). The digital I/O can be configured as either 4 inputs and 12 outputs or 12 inputs and 4 outputs. The outputs are 3.3 volt TTL compatible. The inputs are 5 volt TTL tolerant with pull-up resistors available to 5 volts (not mounted by default).

An alternate configuration for the digital I/O is also available where U20 is changed to a 74LVTH245 transceiver. With this configuration, the choices for the digital I/O are 16 inputs, 8 inputs and 8 outputs, or 16 outputs.

The FPGA controls the interface between the EVM board and the daughterboard. All signal traffic goes through the FPGA except for the address and data lines driving the flash. Only the control lines on the flash are wired to the FPGA. The FPGA can use the address lines from the EVM to decode reads/writes to the flash, to the digital I/O, and to the converters.

On power-up, the FPGA configuration is loaded automatically from the serial PROM (U2) or flash (U9 and/or U10). The FPGA program can then direct the flash to boot-load the DSP. This operation is covered in more detail in the software section of the manual.

Another useful function is preprocessing of the A/D samples before sending them to the DSP. This can greatly reduce the load on the DSP. Processor load can also be reduced by using the DMA to retrieve the samples from the FPGA and writing them directly to memory. The FPGA can control a DSP interrupt which facilitates the DMA transfer to DSP memory. The interrupt is generated once for a frame of data. An example of this can be seen in the sample program.

In addition, all of the lines for the DSP serial ports, DSP clocks, DMA control lines (if any), and the control/status lines from the EVM are available at the FPGA pins.

3.3 A/D Converters and Input Amplifiers

The two channel A/D converters, THS1209 referenced as U5 and U6 in the schematics, are connected to the outputs of four input amplifiers. The dual channel amplifiers, THS4032, are referenced as U100, and U200. The input analog signal can be applied to any of the 4 inputs to the amplifiers through the breadboard area, or if the appropriate user selectable components are installed, the signal can be applied through J3 through J12.

The control signals for the A/D converters are the clock, chip select, write data, read data, and reset driven by the FPGA; sync feeds to the FPGA but should not be used as read strobe. The A/D converter range is 1.5 to 3.5 volts with a reference output at 2.5 volt. For information on changing the A/D reference voltages, refer to the THS1209 data sheet.

Many different input amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-2 shows two non-inverting configurations. The x in the component identification indicates the amplifier used, for example U100a has R100 as the feedback resistor. For U100b, R100 becomes R101. Notice that, for example, RCx20 is a capacitor in some circuits and a resistor in others. See Appendix C for details of the component identification suffix conventions in multi-pad components like Rx12 and Rx14.

Figure 3-3 shows two inverting configurations similar to Figure 3-2. The Biased Inverting Amplifier is very useful in converting a +/- V signal into a 1.5-V to 3.5-V signal suitable for input to the A/D converter. For example, if the input is +/- 1.0 V, and the Reference is 2.5 V, then the output is 1.5 V to 3.5 V. Combining the Biased Unity Gain Buffer with the Biased Inverting Amplifier and driving both with the same input signal results in a singled ended input amplifier with differential biased output.

3.4 D/A Converters and Output Amplifiers

The D/A converters, THS5661, are referenced as U7 and U8 in the schematics. The output amplifiers, THS3001, are referenced as U30 and U31. The FPGA controls the operation of the D/A converter. By driving the CLK pin on the D/A converter, data is clocked into the converter.

The differential current output of each D/A is connected to a pair of resistors that complete the current path and develop a voltage output. These signals may be used to drive a number of output amplifier configurations. The output voltage is up to 1.25 volts.

Many different output amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-4 shows two non-inverting configurations. Figure 3-5 shows two inverting configurations. The outputs of the amplifiers may be connected to output connectors J5 and J8 or to the bread board area . See the schematic in Appendix A for details.

The Differential Input Amplifier is also useful as the output amplifier for using the differential signal from the D/A.

3.5 Digital Buffers

The digital transceivers, U18, U19 and U20, are 74ABT245. They buffer the digital signals between the FPGA and the connector J15. U18 buffers I/O numbers 17-24; U19 buffers I/O numbers 9-16; and U20 buffers I/O numbers 1-8. They can support digital I/O up to 100 MHz. All the buffers can be enabled or disabled, and the directions set by the FPGA in groups of eight.

3.6 Reference Supplies

Three reference supplies are provided, 4.096 V, 2.048 V, and 1.024 V. The 2.048-V and 1.024-V supplies are adjusted with pots R20 and R24. Care must be taken in using these supplies not to overload or put the supply out of calibration. The 4.096-V supply is regulated with a reference diode and can produce 20 mA. The 2.048-V and 1.024-V supplies are not regulated; use of these supplies must be limited to 0.1 mA and must not vary dynamically. If the loads on the references, are dynamically varying, a buffer amplifier should be used on each one.

3.7 Boot Flash Memory (optional)

The flash memory chips, AM29F400B, are referenced as U13 and U14. These do not come standard on the board, but can be purchased as options. These are each 4.0 Megabit, CMOS, 5.0-V only, boot-sector flash memory. They can be written to directly with the DSP. The FPGA is used to provide address selection. The flash can be used to boot-load the DSP on power-up. Refer to the AM29F400B data sheet for details on operation.

3.8 Breadboard Area

The breadboard area was designed for building custom analog circuitry. Adjacent to the breadboard area, J14 provides 20 analog inputs and 8 analog outputs. The 20 analog inputs can be differential or single ended. In the differential mode, the negative side must be wired into the breadboard. In the single ended mode, each wire in the cable has a ground wire between it an the adjoining wire which is grounded with a zero-ohm jumper. Also adjoining the breadboard area are the input and output amplifiers for the converters. The breadboard area was designed for using both through-hole and 50 mil surface-mount components. The breadboard has +/- 9 V available throughout.

Included in Appendix C are enlarged silkscreens and enlarged copper layout of the breadboard area. Because of the small size of components used, the silkscreens do not have all the component labels, but the enlarged silkscreens are complete. Both enlargements are helpful for finding components and test points on the board and are useful for laying out component placement in the planning stage.

3.9 Interfaces

3.9.1 EVM Expansion Connectors

Two 80 pin connectors provide the interface between the EVM and the daughterboard. One expansion connector provides access to the DSP's asynchronous EMIF, and the other provides access to the DSP's peripherals and control/status signals. Both connectors also provide power to the daughterboard. Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the EVM board.⁽¹⁾

The expansion memory interface connector has a reference designator of J6 on the EVM and J9 on the daughterboard. The expansion peripheral interface connector is J7 on the EVM and J10 on the daughterboard. The pinouts are in Tables 3-1 and 3-2 respectively below. The connections on the daughterboard are listed. Of particular interest is the FPGA pin number which must be referenced in FPGA configurations in order the make the proper connections in the FPGA.

Table 3-1. Expansion Memory Interface

Table 3-2. Expansion Peripheral Interface

3.9.2 JTAG Port for FPGA Programming

The JTAG connector is a 14-pin single-row header that has a reference designator of J1 on the daughterboard. When using the JTAG Programmer to load the FPGA configurations, the INIT pin on the FPGA must be pulled low. This is accomplished by placing a jumper between pins 1 and 2 on J1. When loading configurations to the configuration flash, INIT pin does not need to be pulled low. The pin-out for J1 is shown in Table 3-3. The connection to the PC is intended to be made with the Xilinx download cable. Also, the necessary signals are brought to this connector for using Xilinx's Hardware Debugger. When using the Hardware Debugger, see the directions for changing the FPGA mode in the section on Configuration Modes.

Table 3-3. JTAG Port Pin Description (AED-103)

3.9.3 Digital I/O Connector

The digital I/O connector is a 40-pin, 50 mil pitch, double-row connector designated J15. This connector has 24 digital I/Os, 6 grounds, and 10 pins that are connected to pads adjacent to the breadboard area. The pin-out for the connector is shown in Table 3-4 with the FPGA pin which corresponds with the connector pin. The mating connector can be purchased from Samtec. The recommended cable is part number FFSD-20D-1201-N (12 inches long). See section on Digital Buffers for more detail.

Table 3-4. Digital I/O Pin Description

* Use 210 for clock input.

3.9.4 Analog I/O Connector

The analog I/O connector is a 50-pin, 50 mil, double-rowconnector designated J14. The first 20 odd number pins go to the breadboard area. The first 20 even number pins have a position for a ground jumper and/or a pad for wiring. This facilitates single-ended inputs by using the jumper and allows differential inputs by omitting the jumper and using a wire. The remaining pins include two analog grounds and 8 single-ended analog outputs. See the schematics in Appendix A for pin-out. The mating connector can be purchased from Samtec. The recommended cable is part number FFSD-25D-1201-N (12 inches long).

1. TMS320C601/6701 Evaluation Module Technical Reference, (literature number SPRU305), Texas Instruments, 1998.