The Signalware AED-109 daughterboard is designed to provide the user with maximum configuration flexibility. Besides the breadboard area, there are several components which are user selectable. These components are mainly resistors and capacitors that are associated with the amplifiers that drive the A/Ds and are driven by the D/As. They are 0603 size, surface-mount parts to minimize area required. The schematics in Appendix A make clear which components are user selectable.
All components (resistors and capacitors) on sheets AED1097-AED1099 of the schematic are user selectable. This allows for custom amplifier configurations. The components in the schematics, like "CAP3" and "RES3", are physically laid out as three pads. With these pads, one can place one 0603 size component in one of two positions. The silkscreen on the board has a white line between pads 1 and 2 of the component which is position "a"; position "b" uses pads 2 and 3. The "RES4" and "RES5" are like the "RES3" but have 4 and 5 pads in a line respectively. The white line on the silkscreen is also between pins 1 and 2. See Appendix C for details. When your configuration needs a jumper, a zero-ohm resistor should be used.
For testing purposes, some user selectable components have been placed. By default, the board is configured with two single-ended input channels on J3 and J4 which drive A/Ds U5 and U6 in the differential mode. These inputs use a pair of amplifiers to create the differential signal each with a gain of 1, one inverting and one non-inverting to give an overall gain of 2. The outputs of the amplifiers are wired to 2 channels of each A/D converter with a single-pole, low-pass filter on each one with the pole set at 16 MHz. Table 2-1 shows the connections made on a standard board.
Table 2-1. Default Connections for A/D Amplifiers
| Input Connector | Amplifier Ref. # / Operation | A/D Ref. # / Channel | Display Letter |
| J7 | U100A / Inverting | U5 / CH0 | A |
| U100B / Non-inverting | U5 / CH1 | C | |
| J6 | U200A / Inverting | U6 / CH1 | B |
| U200 / Non-inverting | U6 / CH0 | D |
By default, the differential outputs of the D/A converters are each connected to ground by a resister. This generates a pair of differential voltage outputs which are connected to an amplifier with gain of 1, differential input, and single-ended output. The outputs of the amplifiers are connected to the connector J5 and J6. These connections are listed in Table 2-2.
Table 2-2. Default Connections for D/A Amplifiers
| Output Connector | Amplifier Designation | D/A Designation |
| J8 | U300 | U7 |
| J5 | U400 | U8 |
The reference currents for the D/A converters are generated internally by the D/A. These currents may be scaled by varying R327 and R332 respectively for U7 and U8. The effective gain of the converters is determined by the current references and the output resistors R340/R341 and R342/R343 respectively.
The Signalware AED-109 daughterboard uses the THS4032 operational amplifiers to drive the inputs of the A/D converters and the THS3001 operational amplifier to buffer the outputs of the D/A converters. The gain of these amplifiers is set to one, by default, with equal value resistors for the feedback and input resistors. A loading resistor is placed across the input to the A/D amplifiers to reference the input to ground; however, because the inverting amplifiers draw some current, a bias voltage is developed across the input resistor which is evident in the A/D readings when there is no input source. The input range to these amplifiers -1 V to +1 V. The D/A amplifiers output -1 V to +1 V. See Daughterboard Descriptions for more details.
Tools for developing and downloading FPGA configurations are available from Xilinx. The ISE Series Software tools offers both a no cost introductory version (WebPack) and versions with more capability. The basic version will allow reconfiguration of the standard board without FPGA options. Some of the larger FPGA options can only be configured with the more advanced options. FPGA configurations are used to adapt the FPGA to perform its function customized for the application.
There are three methods that can be used to configure the Spartan XL series or the Virtex-E FPGA with its program on the AED-109 daughterboard: 1) use of the serial PROM or flash configuration memory, 2) the JTAG Programmer, or 3) the Hardware Debugger.
1) The nominal method of configuration on the AED-109 board is via the serial configuration memory. For this method, the FPGA must be set to the Master Serial mode with all I/O pins pulled up prior to completion of configuration. This is accomplished with resistors (R1, R2, and R3) that pull down the appropriate mode pins on the FPGA. (For the Spartan XL series, a 4.7k Ohm resistor is used to pull down only the mode pin M0 on R2; for Virtex, only M0 and M1 are pulled down with 0.0 Ohm resistors on R2 and R3 while M2 remains high with an internal pull-up.) In this mode, the FPGA is automatically configured from the serial configuration memory on power-up. This method is good for a final program, but is not convenient when debugging programs.
Either serial PROM (default) or flash configuration memory may be supplied with the board. All optional Virtex FPGAs are supplied with flash as follows:
For boards with serial PROM, the making of a serial PROM is described is in a separate section below; the PROM is then inserted in the daughterboard prior to power up. For boards with flash configuration memory, the flash memory may be programmed on the board with the JTAG Programmer. The flash configuration memory is in the JTAG chain with the FPGA. The board will have either or both of the flash configuration memory devices (U9 or U10) depending of the size of the FPGA mounted on the board.
2) The JTAG Programmer (supplied with Xilinx tools) is the preferred method for configuring the FPGA with its program while debugging. If the daughterboard has flash configuration memory, the JTAG Programmer can also download the FPGA program to flash configuration memory. The flash and the FPGA (in that order) must be configured in a chain in the setup of the JTAG Programmer. The appropriate configuration files must be selected for each device. The JTAG Programmer uses the download cable (also supplied by Xilinx) and the JTAG connector (J1) on the AED-109 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low while using the JTAG Programmer. The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground are also connected to the Xilinx download cable, and the FPGA or flash is ready to program. Refer to the section on JTAG Port for FPGA Programming for the pin-out of J1.
3) The Hardware Debugger (also supplied with Xilinx tools) is a second method for downloading programs to the FPGA while debugging. The pins CCLK, DONE, DIN, PROG, power, and ground on J1 are used with the Hardware Debugger. INIT should not be pulled low as it is when using the JTAG Programmer. The FPGA must be in the Slave Serial mode with I/O pins pulled up prior to completion of configuration. (For the Spartan XL series, all the mode pins are internally pulled high by removing R4; for Virtex, only M2 is pulled down with 0.0 Ohm resistors on R1 while M0 and M2 remain high with an internal pull-up resistors.)
Once a final program is ready to be placed in a serial PROM or flash, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with a Spartan XCS20XL use an XC17S20XLPD8C, with a Spartan XCS30XL use an XC17S30XLPD8C, or with an Spartan XCS40XL use an XC17S40XLPD8C serial PROM. Daughterboards with an XCV50E or XCV200E FPGA may use an XC1701L serial PROM although this is not standard for these devices and some changes in jumpers are necessary.
After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.
The AED-109 daughterboard mounts to the development board's expansion connectors with the breadboard area closest to the back panel. It is crucial that the metric standoffs provided in the mounting kit be used when mounting the daughterboard to the development board. These provide a mating height of 12.0 mm. Using anything smaller than 11.81 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the development board, it should be secured with four M3x.5x6mm metric screws through the mounting holes provided on the development board.
If the development board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off install the development board and daughtercard according to the instructions provided with the development board.
Upon powering up the development board, the FPGA sample program is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "ddddddd_AED109.out"where ddddddd is the designation for the EVM or DSK, can be found in the zip file for the software. For the C6201 EVM, before starting Code Composer Studio, reset the EVM board with the speed option set to 3. This sets the EVM clock speed to 160 MHz. Now load and run the program using Code Composer Studio. For the C6701 EVM, set the board speed to the fastest speed available on that board with speed option set to 3. The speed will depend on the particular board used. For DSKs, the test program is designed to run at the factory set clock speed. The format of the output is described in Figures 2-1 and 2-2.
Figure 2-1. Display Window for AED-109 Test Program
Line| Display Window No.
--- | Content
----+------------------------------------------------------------
001 |** AED 109 TEST PROGRAM STARTED ***
002 |Begin application processing (Block size = zz)
003 |Interrupts received = yy
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb)aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |C= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
015 |D= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
016 |[dd] www www www www www www www www www www www www www www
www www
017 |[dd] www www www www www www www www www www www www www www
www www
018 |[dd] www www www www www www www www www www www www www www
www www
019 |[dd] www www www www www www www www www www www www www www
www www
020 |[dd] www www www www www www www www www www www www www www
www www
021 |[dd] www www www www www www www www www www www www www www
www www
022 |[dd] www www www www www www www www www www www www www www
www www
023 |[dd] www www www www www www www www www www www www www www
www www
024 |[dd] www www www www www www www www www www www www www www
www www
025 |[dd] www www www www www www www www www www www www www www
www www
026 |[dd] www www www www www www www www www www www www www www
www www
027 |[dd] www www www www www www www www www www www www www www
www www
028 |[dd] www www www www www www www www www www www www www www
www www
029 |[dd] www www www www www www www www www www www www www www
www www
030 |[dd] www www www www www www www www www www www www www www
www www
031 |[dd] www www www www www www www www www www www www www www
www www
032 |Checking Digital Outputs ....
033 |OK
034 |
035 |Operating the D/A converters ....
Figure 2-2. Description of Display Window Content
Line|R/O| Explanation of Line Nos.
--- | - | Content
----+--------------------------------------------------------------
001 | R |Indicates EVM board is communicating
002 | R |Ready to start DMA and application processing
002 | - | zz = buffer size in bytes
003 | R |Indicates if data is received from daughterboard
003 | - | yy = number of frame interrupts received
004 | O |A read drop error occured in DMA processing
004 | - | ee = error code (1 = RDROP bit set;
004 | - | -1 = neither RDROP or Frame Complete set)
004 | - | pp = number of buffer last processed
004 | - | cc = DMA transfer count
005 | O |Application program requested termination
005 | - | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | - | mm = number of buffers processed by application
007 | - | rr = number of buffers recieved from DMA
008 | R |Address and block number of each block processed
-011| - | aaaa = hexidecimal value of buffer address
008 | - | bb = number of the block as received from DMA
012 | R |Averages of values from A/D in the columns of each block.
The
-015| - | records contain 16 columns. The averages for the columns
are in
012 | - | separate lines labeled A through P.
012 | - | uuu = unsigned average value for the block
016 | R |Samples (256)from the first buffer of data processed
-031| - | dd = index of first word in row
016 | - | www = hexidecimal value of word
032 | R |Checking digital I/O is in process
033 | R |Processing is terminated
035 | R |Output a different waveform on each D/A continuously.
R = required in display window, O = optional in display window
A voltage can be applied to J3 and J4 to see an output in this test for the standard board. The active input connectors may depend on the input option selected. Every 0.25 millivolts of input voltage will increase the average output by one binary unit. The inputs driving the A/D converters should be no less than -0.3 V and no greater than 5.3 V. Exceeding this range could damage the converters.
Before the OK is printed at the end of the window, the program operates all of the digital I/O on J15. During the printing before the OK, only the digital I/O line 1 is on. Then each of the remaining 23 digital I/O lines is turned on one at a time for a fraction of a second. The OK is printed after the last I/O is on.
The final part of the test is the D/A test. Two sawtooth waves are produced continuously, one with positive slope and one with negative slope. These waveforms can be observed with an oscilloscope on the connector J5 and J6 shown in Table 2-2.