3. DAUGHTERBOARD DESCRIPTION

3.1 Block Diagram

The block diagram in Figure 3-1 shows the major hardware components including optional flash with a hypothetical FPGA program that demonstrates the use of all these components.

The following subsections reference to this block diagram and the schematics in Appendix A.

3.2 FPGA Functions

The FPGA is referenced as U1 on the daughterboard and uses a PQ or HQ 240 package. All of the signals in the EVM external interfaces feed into the FPGA. The FPGA is also connected to the control lines on the flash, and all of the digital lines of the converters. Alternately, the smaller interior footprint referenced as U3 can be used for smaller, optional FPGAs with a PQ/HQ 208 package.

The 24 digital I/O are not shown in Figure 3-1. These connect from the FPGA to the 74ABT245 transceivers (U18, U19 and U20), and then to a 40-pin connector (J15).

The FPGA controls the interface between the EVM board and the daughterboard. All signal traffic goes through the FPGA except for the address and data lines driving the flash. Only the control lines on the flash are wired to the FPGA. The FPGA can use the address lines from the EVM to decode reads/writes to the flash, to the digital I/O, and to the converters. For the C6x01 EVM, the addresses are 0x01400000, 0x01500000, and 0x01600000 respectively.

On power-up, the FPGA configuration is loaded automatically from the serial PROM (U2). The FPGA program can then direct the flash to boot-load the DSP. This operation is covered in more detail in the software section of the manual.

Another useful function is preprocessing of the A/D samples before sending them to the DSP. This can greatly reduce the load on the DSP. Processor load can also be reduced by using the DMA to retrieve the samples from the FPGA and writing them directly to memory. The FPGA can control EXT_INT7 and read the DMA control which facilitates the DMA interface. An example of this can be seen in the sample program.

In addition, all of the lines for the DSP serial ports, DSP clocks, DMA control lines, and the control/status lines from the EVM are available at the FPGA pins.

3.3 A/D Converters and Input Amplifiers

The four input A/D converters, THS1206 referenced as U5, U6, U7, and U8 in the schematics, are connected to the outputs of the input amplifiers. The dual input amplifiers, THS4052, are referenced as U100, U150, U200, U250, U400, U450, U500, and U550. The input analog signal can be applied to any of the 16 inputs to the amplifiers at pads near the breadboard area, or if the default user selectable components are installed, the signal can be applied to the appropriate pin on J14.

The control signals for the A/D converters are the clock, chip select, write, and read that are driven by the FPGA and data available that is sensed by the FPGA. U5 and U6 are attached to one bus and U7 and U8 are attached to a second bus. Table 3-1 shows the FPGA pins that are connected to the A/D converters.

For all A/D converters, the top end reference voltage is set to 3.5 V, and the bottom end reference voltage is set to 1.5 V. For information on adjusting the A/D reference voltages, refer to the THS1206 data sheet.

Table 3-1. A/D Converter Connection to the FPGA Pins

Many different input amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-2 shows two non-inverting configurations, and Figure 3-3 shows two inverting configurations. The x in the component identification indicates the amplifier used, for example the feedback resistor is marked Rx00 in the figure and, in amplifier U100a, the feedback resistor is R100. In U100b, R100 becomes R101. Notice that any 0603 component can be used so that components designated R, RC, or C might be used with a resistor, capacitor, or jumper. See Appendix C for details of the component identification suffix conventions in multi-pad components like Rx12 and Rx16.

The Biased Inverting Amplifier is very useful in converting a +/- V signal into a 1.5-V to 3.5-V signal suitable for input to the A/D converter. For example, if the input is +/- 1.0 V, and the Bias V is 2.5 V, then the output is 1.5 V to 3.5 V with all resistors equal.

3.4 D/A Converters and Output Amplifiers

The AED-106 does not have D/A converters or output amplifiers permanently mounted on the board. The breadboard area can be used to surface mount any D/A converters and output amplifiers which are SOIC type with 50 mil pin spacing.

3.5 Digital Buffers

The digital transceivers, U18, U19 and U20, are 74ABT245. They buffer the digital signals between the FPGA and the connector J15. U18 buffers I/O numbers 17-24; U19 buffers I/O numbers 9-16; and U20 buffers I/O numbers 1-8. They can support digital I/O up to 100 MHz. The buffers can be enabled or disabled all together, and the directions set by the FPGA in groups of eight.

3.6 Reference Supplies

The THS1206 A/D converters contain internal reference supplies which may be used to bias input amplifiers to adjust for input signal offsets appropriately. The maximum current that each A/D reference supply can produce is 250 ua (microamperes).

3.7 Flash Memory (optional)

The flash memory chips, AM29F400B, are referenced as U13 and U14. These do not come standard on the board, but can be purchased as options. These are each 4.0 Megabit, CMOS, 5.0-V only, boot-sector flash memory. They can be written to directly with the DSP. The FPGA is used to insert wait states into the read/write cycles. The flash can be used to boot-load the DSP on power-up. The example program provided does not provide for the interface to the Flash memory. This function can be programmed into the FPGA by the user. Refer to the AM29F400B data sheet for details on operation.

3.8 Breadboard Area

The breadboard area was designed for building custom analog circuitry. Adjacent to the breadboard area, J14 provides 20 analog inputs and 8 analog outputs. The 20 analog inputs can be differential or single ended. In the differential mode, the negative side must be wired into the breadboard. In the single ended mode, each wire in the cable has a ground wire between it an the adjoining wire which is grounded with a zero-ohm jumper. Also adjoining the breadboard area are the input and output amplifiers for the converters. The breadboard area was designed for using both through-hole and 50 mil surface-mount components. The breadboard has +/- 9 V available throughout.

Included in Appendix C are enlarged silkscreens and enlarged copper layout of the breadboard area. Because of the small size of components used, the silkscreens do not have all the component labels, but the enlarged silkscreens are complete. Both enlargements are helpful for finding components and test points on the board and are useful for laying out component placement in the planning stage.

3.9 Interfaces

3.9.1 EVM Expansion Connectors

Two 80 pin connectors provide the interface between the EVM and the daughterboard. One expansion connector provides access to the DSP's asynchronous EMIF, and the other provides access to the DSP's peripherals and control/status signals. Both connectors also provide power to the daughterboard. Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the EVM board.⁽¹⁾

The expansion memory interface connector has a reference designator of J6 on the EVM and J9 on the daughterboard. The expansion peripheral interface connector is J7 on the EVM and J10 on the daughterboard. The pinouts are in Tables 3-1 and 3-2 respectively below. The connections on the daughterboard are listed. Of particular interest is the FPGA pin number which must be referenced in FPGA configurations in order the make the proper connections in the FPGA.

Table 3-2. Expansion Memory Interface

Table 3-3. Expansion Peripheral Interface

3.9.2 JTAG Port for FPGA Programming

The JTAG connector is a 14-pin single-row header that has a reference designator of J1 on the daughterboard. When using the JTAG Programmer to load the FPGA configurations, the INIT pin on the FPGA must be pulled low. This is accomplished by placing a jumper between pins 1 and 2 on J1. The pin-out for J1 is shown in Table 3-3. The connection to the PC is intended to be made with the Xilinx download cable. Also, the necessary signals are brought to this connector for using Xilinx's Hardware Debugger. When using the Hardware Debugger, see the directions for changing the FPGA mode in the section on Configuration Modes.

3.9.3 Digital I/O Connector

The digital I/O connector is a 40-pin, 50 mil pitch, double-row connector designated J15. This connector has 24 digital I/Os, 6 grounds, and 10 pins that are connected to pads adjacent to the breadboard area. The pin-out for the connector is shown in Table 3-4 with the FPGA pin which corresponds with the connector pin. The mating connector can be purchased from Samtec. The recommended cable is part number FFSD-20D-1201-N (12 inches long). See section on Digital Buffers for more detail.

* Use 210 for clock input.

3.9.4 Analog I/O Connector

The analog I/O connector is a 50-pin, 50 mil, double-row connector designated J14. The first 20 odd number pins go to the breadboard area. The first 20 even number pins have a position for a ground jumper and/or a pad for wiring. This facilitates single-ended inputs by using the jumper and allows differential inputs by omitting the jumper and using a wire. The remaining pins include two analog grounds and 8 single-ended unused analog I/0. See the schematics in Appendix A for pin-out. The mating connector can be purchased from Samtec. The recommended cable is part number FFSD-25D-1201-N (12 inches long).

1. TMS320C601/6701 Evaluation Module Technical Reference, (literature number SPRU305), Texas Instruments, 1998.