2. CONFIGURATION AND INSTALLATION

2.1 User Selected Components

The Signalware AED-106 daughterboard is designed to provide the user with maximum configuration flexibility. Besides the breadboard area, there are several components which are user selectable. These components are mainly resistors and capacitors that are associated with the amplifiers that drive the A/Ds. They are 0603 size, surface-mount parts to minimize area required. The schematics in Appendix A make clear which components are user selectable.

All components (resistors and capacitors) on sheets AED1065-AED10612 of the schematic are user selectable. This allows for custom amplifier configurations. The components in the schematics, like "CAP3" and "RES3", are physically laid out as three pads. With these pads, one 0603 size component can be placed in one of two positions. The silkscreen on the board has a white line between pads 1 and 2 of the component which is position "a"; position "b" uses pads 2 and 3. The "RES4" and "RES5" are like the "RES3" but have 4 and 5 pads in a line respectively. The white line on the silkscreen is also between pins 1 and 2. See Appendix C for details. When the configuration needs a jumper, a zero-ohm resistor should be used.

For testing purposes, some user selectable components have been placed. By default, the board is configured with 16 pins of J14 connected to 16 amplifiers, which have a gain of 1. The outputs of the amplifiers are wired to 4 channels of each A/D converter. The connections from the amplifiers to the connector are made with zero-ohm resistors in the breadboard area. Table 2-1 shows the connections made on a standard board.

Table 2-1. Default Connections for A/D Amplifiers

2.1.1 Amplifiers

The Signalware AED-106 daughterboard uses the THS4052 operational amplifiers to drive the inputs of the A/D converters. By default, the gain of these amplifiers is st to one. They are inverting, and they are supplied a reference to shift the input by +2.5V. A 49.9 ohm resistor is placed on the input of the amplifier to provide loading and ground reference. The input range to these amplifiers -1.0 V to +1.0 V. Figure 2-1 shows the default amplifier configuration.

2.2 FPGA Programming

Tools for developing and downloading FPGA programs are available from Xilinx. The Foundation Series Software tools offers both a low cost introductory version (basic) and a full capability version. (SIGNALWARE supplies schematics compatible with the standard Foundation tools; ISE tools are not supported.) The basic version will program the standard board and some limited number of FPGA options. FPGA programs are used to configure the FPGA to perform its customized function.

2.2.1 Configuration Modes

There are three methods that can be used to configure the Xilinx 4000XL/XLA series or the Virtex FPGA with its program on the AED-106 daughterboard: 1) use of the serial PROM or flash configuration memory, 2) the JTAG Programmer, or 3) the Hardware Debugger.

1) The nominal method of configuration on the AED-106 board is via the serial configuration memory. For this method, the FPGA must be set to the Master Serial mode with all I/O pins pulled up prior to completion of configuration. This is accomplished with resistors (R1, R2, and R3) that pull down the appropriate mode pins on the FPGA. (For the 4000XL/XLA series, 4.7k Ohm resistors are used for all the mode pins; for Virtex, only M0 and M1 are pulled down with 0.0 Ohm resistors on R2 and R3 while M2 remains high with an internal pull-up.) In this mode, the FPGA is automatically configured from the serial configuration memory on power-up. This method is good for a final program, but is not convenient when debugging programs.

Either serial PROM or flash configuration memory may be supplied with the board. For boards with serial PROM, the making of a serial PROM is described in a separate section below; the PROM is then inserted in a socket on the daughterboard prior to power up. For boards with flash configuration memory, the flash memory may be programmed on the board with the JTAG Programmer. The flash configuration memory is in the JTAG chain with the FPGA. The board will have either or both of the flash configuration memory devices (U9 or U10) depending of the FPGA mounted on the board.

2) The JTAG Programmer (supplied with Xilinx tools) is the preferred method for configuring the FPGA with its program while debugging. If the daughterboard has flash configuration memory, the JTAG Programmer can also download the FPGA program to flash configuration memory. The flash and the FPGA (in that order) must be configured in a chain in the setup of the JTAG Programmer. The appropriate configuration files must be selected for each device. The JTAG Programmer uses the download cable (also supplied by Xilinx) and the JTAG connector (J1) on the AED-106 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low while using the JTAG Programmer. The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground are also connected to the Xilinx download cable, and the FPGA or flash is ready to program. Refer to the section on JTAG Port for FPGA Programming for the pin-out of J1.

3) The Hardware Debugger (also supplied with Xilinx tools) is a second method for downloading programs to the FPGA while debugging. The pins CCLK, DONE, DIN, PROG, power, and ground on J1 are used with the Hardware Debugger. INIT should not be pulled low as it is when using the JTAG Programmer. The FPGA must be in the Slave Serial mode with I/O pins pulled up prior to completion of configuration. (For the 4000XL/XLA series, all the mode pins are internally pulled high by removing R4; for Virtex, only M2 is pulled down with 0.0 Ohm resistors on R1 while M0 and M2 remain high with an internal pull-up resistors.)

2.2.2 Making a Serial PROM

Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with an XC4010XL, XC4013XL/XLA, or XC4020XL/XLA FPGA use an XC17512L serial PROM. Daughterboards with an XC4044XL/XLA, XCV50, XCV100, or XCV150 FPGA use an XC1701L serial PROM.

After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.

2.3 Mounting Daughterboard on EVM

The AED-106 daughterboard mounts to the EVM's expansion connectors with the breadboard area closest to the back panel. It is crucial that the standoffs provided be used when mounting the daughterboard to the EVM board. These provide a mating height of 12.0 mm. Using anything smaller than 11.81 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the EVM board, it should be secured with four M3x.5x6mm screws and washers through the mounting holes provided on the EVM board.

2.4 Running the Test Program

If the EVM board has not been previously installed in the PC, install the drivers and the Code Composer Studio software. Then with the power off install the EVM and daughtercard.

Upon powering up the EVM board, the FPGA sample program is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "aed106.out", can be found on the provided floppy disk. Before loading the program on the C6x01 EVM, reset the EVM board with the speed option set to 3. (Use EVM6XRST.bat with the .exe line including "-s3".) This sets the EVM clock speed to 160 MHz. Now load and run the program using Code Composer Studio. The format of the output is described in Figures 2-2 and 2-3.

A voltage can be applied to the following pins of J14 to see an output in this test: Pin 15, 17, 13, 9, 27, 33, 23, 1, 29, 37, 25, 11, 35, 31, and 21. All 16 channels from the A/Ds are sampled and displayed in columns. Every 0.488 mV of input voltage will increase the output by one binary unit. Full scale range for an input to the amplifiers is -1V to +1 V. The output of the amplifiers driving the A/D converters should be no less than -0.3 V and no greater than 5.3 V. This corresponds with an amplifier input range of -2.8 V to +2.8 V. Exceeding this range could damage the converters.

Figure 2-2. Display Window for AED-106 Test Program

Line| Display Window
No. | Content
----+------------------------------------------------------------

001 |*** AED TEST PROGRAM STARTED ***
002 |Buffer Allocation Error [ssXyy]
003 |Begin application processing (Buffer size = zz)
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |C= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
015 |D= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
016 |E= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
017 |F= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
018 |G= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
019 |H= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
020 |I= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
021 |J= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
022 |K= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
023 |L= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
024 |M= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
025 |N= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
026 |O= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
027 |P= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
028 |[dd] www www www www www www www www www www www www www www www www
029 |[dd] www www www www www www www www www www www www www www www www
030 |[dd] www www www www www www www www www www www www www www www www
031 |[dd] www www www www www www www www www www www www www www www www
032 |[dd] www www www www www www www www www www www www www www www www
033 |[dd] www www www www www www www www www www www www www www www www
034 |[dd] www www www www www www www www www www www www www www www www
035 |[dd] www www www www www www www www www www www www www www www www
036 |[dd] www www www www www www www www www www www www www www www www
037 |[dd] www www www www www www www www www www www www www www www www
038 |[dd] www www www www www www www www www www www www www www www www
039 |[dd] www www www www www www www www www www www www www www www www
040 |[dd] www www www www www www www www www www www www www www www www
041 |[dd] www www www www www www www www www www www www www www www www
042 |[dd] www www www www www www www www www www www www www www www www
043 |[dd] www www www www www www www www www www www www www www www www
044 |OK

Figure 2-3. Description of Display Window Content

Line|R/O| Explanation of Line
Nos.| - | Content
----+---+--------------------------------------------------------------

001 | R |Indicates EVM board is communicating
002 | O |Buffers could not be allocated in heap (teminates program)
002 | O | ss = size of each buffer in bytes
002 | O | yy = number of buffers required
003 | R |Ready to start DMA and application processing
003 | R | zz = buffer size in bytes
004 | O |A "read drop error" occured in DMA processing
004 | O | ee = error code (1 = RDROP bit set;
004 | O | -1 = neither RDROP or Frame Complete set)
004 | O | pp = number of buffer last processed
004 | O | cc = DMA transfer count
005 | O |Application program requested termination
005 | O | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | R | mm = number of buffers processed by application
007 | R | rr = number of buffers recieved from DMA
008 | R |Address and block number of each block processed
-011| R |
008 | R | aaaa = hexidecimal value of buffer address
008 | R | bb = number of the block as received from DMA
012 | R |Averages of values from A/D in the columns of each block. The
-027| R |
012 | R | records contain 16 columns. The averages for the columns are in
012 | R | separate lines labeled A through P.
012 | R | uuu = unsigned average value for the block
028 | R |Samples (256) from the first buffer of data processed
-043| R |
028 | R | dd = index of first word in row
028 | R | www = hexidecimal value of word
044 | R |Processing is terminated

R = required in display window, O = optional in display window

Before the OK is printed at the end of the window, the program operates all of the digital I/O on J15. During the printing before the OK, only the digital I/O line 1 is on. Then each of the remaining 23 digital I/O lines is turned on one at a time for about 1 second. Finally, the OK is printed.