2. CONFIGURATION AND INSTALLATION

2.1 User Selected Components

The Signalware AED-102 daughterboard is designed to provide the user with maximum configuration flexibility. Besides the breadboard area, there are several components which are user selectable. These components are mainly resistors and capacitors that are associated with the amplifiers that drive the A/Ds and are driven by the D/As. They are 0603 size, surface-mount parts to minimize area required. The schematics in Appendix A make clear which components are user selectable.

All components (resistors and capacitors) on sheets AED1021-AED1026 of the schematic are user selectable. This allows for custom amplifier configurations. The components in the schematics, like "CAP3" and "RES3" are physically laid out as three pads. With these pads, one can place one 0603 size component in one of two positions. The silkscreen on the board has a white line between pads 1 and 2 of the component which is position "a"; position "b" uses pads 2 and 3. When the configuration needs a jumper, a zero-ohm resistor should be used. The "RES4" and "RES5" are like the "RES3", but it has 4 and 5 pads in a line respectively. The white line on the silk screen is also between pins 1 and 2. See Appendix C for details.

For testing purposes, some user selectable components have been placed. The board is configured with 16 pins of J14 connected to 16 amplifiers, which have a gain of 1. The outputs of the amplifiers are wired to 16 channels of the A/D converters. Some of the amplifiers are wired to two converters (U5 and U11). The connections from the amplifiers to the connector are made with zero-ohm jumpers in the breadboard area. Table 2-1 shows the connections made on a standard board.

Table 2-1. Default Connections for A/D Amplifiers

The D/A converters are wired to amplifiers with gain 1. The outputs of the amplifiers are wired to the connector J14 with zero-ohm jumpers in the breadboard area. These connections are listed in Table 2-2.

Table 2-2. Default Connections for D/A Amplifiers

2.1.1 D/A References

The reference voltages for the D/A are selected by default to be 2.048 volts. The reference voltage is supplied to two reference input on each of two D/A converters; the maximum output of the converter is 4.096. These voltages may be changed by removing R72, R73, R82, and/or R83 jumpers and wiring the desired voltage to B51, B56, B70, and/or B72.

2.1.2 Amplifiers

The Signalware AED-102 daughterboard uses TL054 operational amplifiers to drive the inputs of the A/D converters and buffer the outputs of the D/A converters. The gain of these amplifiers is set to one, non-inverting, by default with a jumper for the feedback resistor. A loading resistor is placed across the input to the A/D amplifiers to reference the input to ground. The input range to these amplifiers is 0 V to 4.096 V. The D/A amplifiers output 0 V to 4.096 V. See Daughterboard Description chapter for more details on alternate configurations.

2.2 FPGA Programming

Tools for developing and downloading FPGA programs are available from Xilinx. The Foundation series of tools offers both a low cost introductory version (basic) and a full capability version. The basic version will program the standard board without FPGA options.

2.2.1 Configuration Modes

There are three methods that can be used to program the Xilinx 4000XLA series FPGA on the AED-102 daughterboard: use of the serial PROM, the JTAG Programmer, or the hardware debugger.

The default method of configuration on the AED-102 board is via the serial PROM. For this method, the FPGA must be set to the master serial mode. This is accomplished with the 4.7k Ohm resistors (R1, R2, and R3) that pull the mode pins on the FPGA low. In this mode, the FPGA is automatically configured from the serial PROM on power-up. This method is good for a final program, but is not convenient when debugging programs.

The JTAG Programmer (supplied with Xilinx tools) is one method for downloading programs to the FPGA while debugging. The JTAG Programmer uses the download cable (also supplied by Xilinx) and the JTAG connector (J1) on the AED-102 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low. The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground can then be connected to the Xilinx download cable, and the FPGA is ready to program. Refer to Section 3.9.2 for the pin-out of J1.

The Hardware Debugger (also supplied with Xilinx tools) is a second method for downloading programs to the FPGA while debugging. The pins CCLK, DONE, DIN, PROG, power, and ground on J1 are used with the hardware debugger. INIT should not be pulled low as it is when using the JTAG programmer. The zero-ohm jumper, R4, needs to be removed. This allows the mode pins on the FPGA to be internally pulled up so that the FPGA programs in the Slave Serial mode.

2.2.2 Making a Serial PROM

Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with an XC4013XLA, or XC4020XLA FPGA use an XC17512L serial PROM. Daughterboards with an XC4044XLA FPGA use an XC1701L serial PROM.

After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.

2.3 Mounting Daughterboard on EVM

The AED-102 daughterboard mounts to the EVM's expansion connectors with the breadboard area closest to the back panel. It is crucial that the 12 mm metric standoffs provided be used when mounting the daughterboard to the EVM board. Using anything smaller than 11.81 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the EVM board, it should be secured with four M3x.5x6mm screws through the four mounting holes provided on the EVM board. The four holes on the daughterboard have the standoffs mounted at the factory.

2.4 Running the Test Program

If the EVM board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off install the EVM and daughtercard.

Upon powering up the EVM board, the FPGA sample program is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "aed102.out", can be found on the provided floppy disk. Before loading the program, reset the EVM board with the default speed option. This sets the EVM clock speed to 133 MHz. Now load and run the program using Code Composer Studio. The format of the output is described in Figures 2-1 and 2-2.

Figure 2-1. Display Window for AED-102 Test Program

Line| Display Window
No. | Content
----+-----------------------------------------------------------

001 |*** AED TEST PROGRAM STARTED ***
002 |Buffer Allocation Error [ssXyy]
003 |Begin application processing (Buffer size = zz)
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |C= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
015 |D= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
016 |E= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
017 |F= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
018 |G= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
019 |H= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
020 |I= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
021 |[dd] www www www www www www www www www www www www www www www www
022 |[dd] www www www www www www www www www www www www www www www www
023 |[dd] www www www www www www www www www www www www www www www www
024 |[dd] www www www www www www www www www www www www www www www www
025 |[dd] www www www www www www www www www www www www www www www www
026 |[dd] www www www www www www www www www www www www www www www www
027 |[dd] www www www www www www www www www www www www www www www www
028 |[dd] www www www www www www www www www www www www www www www www
029 |[dd] www www www www www www www www www www www www www www www www
030 |[dd] www www www www www www www www www www www www www www www www
031 |[dd] www www www www www www www www www www www www www www www www
032 |[dd] www www www www www www www www www www www www www www www www
033 |[dd] www www www www www www www www www www www www www www www www
034 |[dd] www www www www www www www www www www www www www www www www
034 |[dd] www www www www www www www www www www www www www www www www
036 |[dd] www www www www www www www www www www www www www www www www
037 |OK

Figure 2-2. Description of Display Window Content

Line|R/O| Explanation of Line
Nos.| - | Content
----+---+--------------------------------------------------------------

001 | R |Indicates EVM board is communicating
002 | O |Buffers could not be allocated in heap (teminates program)
002 | O | ss = size of each buffer in bytes
002 | O | yy = number of buffers required
003 | R |Ready to start DMA and application processing
003 | R | zz = buffer size in bytes
004 | O |A "read drop error" occured in DMA processing
004 | O | ee = error code (1 = RDROP bit set;
004 | O | -1 = neither RDROP or Frame Complete set)
004 | O | pp = number of buffer last processed
004 | O | cc = DMA transfer count
005 | O |Application program requested termination
005 | O | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | R | mm = number of buffers processed by application
007 | R | rr = number of buffers recieved from DMA
008 | R |Address and block number of each block processed
-011| R |
008 | R | aaaa = hexidecimal value of buffer address
008 | R | bb = number of the block as received from DMA
012 | R |Averages of values from A/D in the columns of each block. The
-020| R |
012 | R | records contain 16 columns. The averages for the columns are in
012 | R | separate lines labeled A through P.
012 | R | uuu = unsigned average value for the block
021 | R |Samples (256) from the first buffer of data processed
-036| R |
021 | R | dd = index of first word in row
021 | R | www = hexidecimal value of word
037 | R |Processing is terminated

R = required in display window, O = optional in display window

A voltage can be applied to the following pins of J14 to see an output in this test: Pin 15, 17, 13, 9, 25, 11, 35, 31, and 21 in order on the display. These nine channels from the A/Ds are sampled and displayed in columns. See Table 2-1 for the corresponding letter in the display. Every 1 mV of input voltage will increase the output by one hex value. The output of the amplifiers driving the A/D converters should be no less than -0.3 Volts and no greater than 5.3 Volts. Exceeding this range could damage the converters.

Before the OK at the end of the window, the program operates all of the digital I/O on J15. During the printing, line 1 only is on. Then each of the remaining 23 lines is turned on one at a time for about 1 second. Finally, the OK is printed.