3. DAUGHTERBOARD DESCRIPTION

3.1 Block Diagram

The block diagram in Figure 3-1 shows the major hardware components including optional flash with a hypothetical FPGA program that demonstrates the use of all these components.

Figure 3-1. AED-101 Block Diagram

The following subsections reference this block diagram and the schematics in Appendix A.

3.2 FPGA Functions

The FPGA is referenced as U1 on the daughterboard, and uses a PQ or HQ 240 package. Nearly all of the signals in the EVM/DSK external interfaces feed into the FPGA. The FPGA is connected to bits 2-5 and 14-21 of the DSP's EMIF address bus. The FPGA is also connected to the control lines on the flash, and all of the digital lines of the converters. Alternately, the smaller interior footprint referenced as U3 can be used for smaller, optional FPGAs with a PQ/HQ 208 package.

The 16 digital I/O are not shown in Figure 3-1. These connect from the FPGA to two 74LVTH245 transceivers (U19 and U20), and then to a 40-pin connector (J15). The digital I/O can be configured as 16 inputs, 16 outputs, or 8 inputs and 8 outputs. The outputs are 3.3 volt TTL compatible. The inputs are 5 volt TTL tolerant with pull-up resistors available to 5 volts (not mounted by default).

An alternate configuration for the digital I/O is also available where U20 is changed to a 74LVTH244 buffer/driver. With this configuration, the choices for the digital I/O are 12 inputs and 4 outputs, or 4 inputs and 12 outputs.

The FPGA controls the interface between the EVM/DSK board and the daughterboard. All signal traffic goes through the FPGA except for the address and data lines driving the flash. Only the control lines on the flash are wired to the FPGA. The FPGA can use the address lines from the EVM/DSK to decode reads/writes to the flash, digital I/O, and the converters.

On power-up, the FPGA configuration is loaded automatically from the serial PROM (U2) or flash (U9 and/or U10). The FPGA program can then direct the optional boot-flash to boot-load the DSP. This operation is covered in more detail in the software section of the manual.

Another useful function is preprocessing of the A/D samples before sending them to the DSP. This can greatly reduce the load on the DSP. Processor load can also be reduced by using the DMA to retrieve the samples from the FPGA and writing them directly to memory. The FPGA can control a DSP interrupt which facilitates the DMA transfer to DSP memory. The interrupt is generated once for a frame of data. An example of this can be seen in the example program.

In addition, all of the lines for the DSP serial ports, DSP clocks, DMA control lines (if any), and the control/status lines from the EVM are available at the FPGA pins.

3.3 A/D Converters and Input Amplifiers

The single channel A/D converters, ADS80xY, referenced as U5 and U6 in the schematics, are connected to the outputs of four input amplifiers (each A/D has a positive and negative input). The current feedback op-amps, OPA685, are referenced as U100, U101, U200, and U201. The input analog signals can be applied to any of the 4 input amplifiers through the breadboard area, or if the appropriate user selectable components are installed, the signals can be applied through J7, J6, J11, and J4.

The FPGA drives the differential clock for the A/D converters using the LVPECL standard. The A/Ds send a data valid pulse back to the FPGA for synchronization. The A/D converter range is 1.5 V to 3.5 V with a reference output at 2.5 V. For information on changing the A/D reference voltages, refer to the ADS80xY data sheet.

Many different input amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-2 shows two non-inverting configurations. Another useful input filter is the Sallen-Key. An example of that configuration is shown for an output amplifier in figure 3-4. A third pole can also be added at the output of the amplifier, as in figure 3-3. The x in the component identification indicates the amplifier used, for example U100 has R100 as the feedback resistor. For U101, R100 becomes R101. See Appendix C for details of the component identification suffix conventions in multi-pad components like Rx12 and Rx14.

Figure 3-3 shows two inverting configurations similar to Figure 3-2. The Biased Inverting Amplifier is very useful in converting a +/- V signal into a 1.5-V to 3.5-V signal suitable for input to the A/D converter. For example, if the input is +/- 1.0 V, and the Reference is 2.5 V, then the output is 1.5 V to 3.5 V if the gain is set to one. One way to generate a differential biased output from a single-ended input is to drive both the Biased Unity Gain Buffer and the Biased Inverting Amplifier with the same input signal.

3.4 D/A Converters and Output Amplifiers

The D/A converters, THS5661, are referenced as U7 and U8 in the schematics. The output amplifiers, THS3001, are referenced as U300 and U400. The FPGA controls the operation of the D/A converter. By driving the CLK pin on the D/A converter, data is latched into the converter.

The differential current output of each D/A is connected to a pair of resistors that complete the current path and develop a voltage output. These signals may be used to drive a number of output amplifier configurations. The output voltage is up to 1.25 volts.

Many different output amplifier circuits can be created using the 0603 size component locations surrounding each amplifier. Figure 3-4 shows two non-inverting configurations. Figure 3-5 shows two inverting configurations. The outputs of the amplifiers may be connected to output connectors J5 and J8 or to the bread board area . See the schematic in Appendix A for details.

The differential output amplifier is useful for converting the differential signal from the D/A to a single-ended output. This is the default setup.

3.5 Digital Buffers

The digital transceivers, U19 and U20, are 74LVTH245. They buffer the digital signals between the FPGA and the connector J15. U19 buffers I/O numbers 9-16; and U20 buffers I/O numbers 1-8. They can support digital I/O up to 100 MHz. The FPGA can enable or disable the buffers, and set the directions in groups of eight.

3.6 User LEDs

The AED-101 board has four user LEDs that are wired to the Virtex-E FPGA. These LEDs are 0603 sized surface mount components, and they are located together on the back of the board near J15. The FPGA can be configured to control these LEDs with any internal signal. An example would be to connect the FIFO overflow and underflow to LEDs. These could also be memory mapped so that the DSP could control them. The LEDs are active low, so putting a logic low on the appropriate FPGA pin will cause the LED to light. The following table shows the FPGA connections to the LEDs.

Table 3-1. FPGA Connections to User LEDs

3.7 Reference Supplies

Three reference supplies are provided, 4.096 V, 2.048 V, and 1.024 V. The 2.048-V and 1.024-V supplies are adjusted with pots R20 and R24. Care must be taken in using these supplies not to overload or put the supply out of calibration. The 4.096-V supply is regulated with a reference diode and can produce 20 mA. The 2.048-V and 1.024-V supplies are not regulated; use of these supplies must be limited to 0.1 mA and must not vary dynamically. If the loads on the references are dynamically varying or require more than 0.1 mA, a buffer amplifier should be used on each one.

3.8 Boot Flash Memory (optional)

The flash memory chips, AM29LV400B, are referenced as U13 and U14. These do not come standard on the board, but can be purchased as options. These are each 4.0 Megabit, CMOS, 3.3-V only, boot-sector flash memory. They can be written to directly with the DSP. The FPGA is used to provide chip enables, and the address bus is connected directly to bits 2-19 of the DSP's EMIF address bus. The data bus on the flash is connected directly to the DSP's EMIF data bus. The flash can be used to boot-load the DSP on power-up. Refer to the AM29LV400B data sheet for details on operation.

3.9 Breadboard Area

The breadboard area was designed for building custom analog circuitry. Also adjoining the breadboard area are the input and output amplifiers for the converters. The breadboard area was designed for using both through-hole and 50 mil surface-mount components. The breadboard has regulated +/- 9 V available throughout.

Included in Appendix C are enlarged silkscreens and enlarged copper layout of the breadboard area. Because of the small size of components used, the silkscreens do not have all the component labels, but the enlarged silkscreens are complete. Enlargements are helpful for finding components and test points on the board. They are also useful for laying out component placement in the planning stage.

Adjacent to the breadboard area are eight SMB connectors which provide 8 analog inputs or outputs. The analog inputs/outputs can be differential or single-ended. In the differential mode, there are two ways of using the SMB connectors. For a floating coax, the negative side is wired to the shell of the SMB connector. For dual coax, the negative side is wired to a separate SMB connector. In this case, each differential analog signal uses two SMB connectors, and the shells of the connectors should be grounded. In the single ended mode, each analog signal uses one SMB connector, and the shell of the connector is grounded.

3.10 Interfaces

3.10.1 EVM Expansion Connectors

Two 80 pin connectors provide the interface between the EVM/DSK and the daughterboard. One expansion connector provides access to the DSP's asynchronous EMIF, and the other provides access to the DSP's peripherals and control/status signals. Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the EVM/DSK board.⁽¹⁾ Both connectors also provide power to the daughterboard. Most DSK boards do not provide +12 V and -12 V, which are needed by the daughterboard. In these cases, the user must supply these voltages with an external power supply. DSKs usually have a dedicated 4 pin connector for this purpose. Consult the documentation of the DSK to find out if an external supply is needed, and if so, how to connect it.

The pinouts are in Tables 3-1 and 3-2 respectively below. The connections on the daughterboard are listed. Of particular interest is the FPGA pin number which must be referenced in FPGA user constraint file in order the make the proper connections in the FPGA.

Table 3-2. Expansion Memory Interface

Table 3-3. Expansion Peripheral Interface

3.10.2 JTAG Port for FPGA Programming

The JTAG connector is a 14-pin single-row header that has a reference designator of J1 on the daughterboard. When using the Xilinx programmer, iMPACT, to load the FPGA configurations into the FPGA, the INIT pin on the FPGA must be pulled low. This is accomplished by placing a jumper between pins 1 and 2 on J1. When loading configurations to the configuration flash, INIT pin does not need to be pulled low. For more information, see section 2.2. The pin-out for J1 is shown in Table 3-3. The connection to the PC is intended to be made with the Xilinx or Insight download cable.

Table 3-4. JTAG Port Pin Description (AED-101)

3.10.3 Digital I/O Connector

The digital I/O connector is a 40-pin, 50 mil pitch, double-row connector designated J15. This connector has 16 digital I/Os, 6 grounds, and 18 pins that are connected to pads adjacent to the breadboard area. The pin-out for the connector is shown in Table 3-4 with the FPGA pin which corresponds with the connector pin. The mating connector can be purchased from Samtec. The recommended cable is part number FFSD-20D-1201-N (12 inches long). See section on Digital Buffers for more detail.

Table 3-5. Digital I/O Pin Description

* Use 210 for clock input.

Figure 3-6. Orientation of Digital Connector

3.10.4 Analog I/O Connector

The analog I/O can be connected through 8 SMB or SMA connectors. The analog inputs/outputs can be differential or single-ended. In the differential mode, there are two ways of using the SMB connectors. For a floating coax, the negative side is wired to the shell of the SMB connector. For dual coax, the negative side is wired to a separate SMB connector. In this case, each differential analog signal uses two SMB connectors, and the shells of the connectors should be grounded. In the single ended mode, each analog signal uses one SMB connector, and the shell of the connector is grounded. See the schematics in Appendix A for wiring.

Table 3-6. SMB/SMA Connectors

1. TMS320 Cross-Platform Daughtercard Specification, (literature number SPRA711), Texas Instruments, 2000.