2. CONFIGURATION AND INSTALLATION

2.1 User Selected Components

The Signalware AED-101 daughterboard is designed to provide the user with maximum configuration flexibility. Besides the breadboard area, there are several components which are user selectable. These components are mainly resistors and capacitors that are associated with the amplifiers that drive the A/Ds and are driven by the D/As. They are 0603 size, surface-mount parts to minimize area required. The schematics in Appendix A make clear which components are user selectable.

All components with a * (resistors and capacitors) on sheets AED1017-AED1019 of the schematic are user selectable. This allows for custom amplifier configurations. The components in the schematics, like "CAP3" and "RES3", are physically laid out as three pads. With these pads, you can place one 0603 size component in one of two positions. The silkscreen on the board has a white line between pads 1 and 2 of the component which is position "a"; position "b" uses pads 2 and 3. The "RES4" and "RES5" are like the "RES3" but have 4 and 5 pads in a line respectively. The white line on the silkscreen is also between pins 1 and 2. See Appendix C for details. When your configuration needs a jumper, a zero-ohm resistor should be used.

For testing purposes, some user selectable components have been placed. By default, the board is configured with two single-ended AC input channels on J7 and J6 which drive A/Ds U5 and U6. These inputs use a single inverting amplifier with a gain of 2. The outputs of the amplifiers are wired to the positive inputs of each A/D converter with a single-pole, low-pass filter on each one with the pole set at 300 MHz. The negative input of the A/D converter is tied to the 2.5 Volt reference. The maximum voltage input on the SMB connectors is1 Volt Peak-to-Peak. After amplification and level shifting, the A/D converter will see 2 Volts Peak-to-Peak centered at 2.5 Volts. Table 2-1 shows the connections made on a standard board.

Table 2-1. Default Connections for A/D Amplifiers

We also suggest that you take advantage of the location provided for adding a shunt capacitor at the input to the A/D to limit the bandwidth. By default, placed a 10 pF capacitor is placed at that location (C107 and C207). We find that if your anti-aliasing filter is any even number of poles, this additional one real pole filter works out well to give you a good overall combination of filters. For most filters, the single real pole is very near or less than the end of the filter pass band. This means that the signal gets pre-emphasis at the high end before the amplifier, and is cut after the amplifier to give a flat response. This minimizes the effect of amplifier noise.

By default, the differential outputs of the D/A converters are each connected to ground by a 51.1 Ohm resister. This generates a pair of differential voltage outputs which are connected to an amplifier with gain of 1, differential input, and single-ended output. The outputs of the amplifiers are connected to the connector J8 and J5. These connections are listed in Table 2-2.

Table 2-2. Default Connections for D/A Amplifiers

2.1.1 D/A References

The reference currents for the D/A converters are generated internally by the D/A. These currents may be scaled by varying R327 and R332 respectively for U7 and U8. The effective gain of the converters is determined by the current references and the output resistors R340/R342 and R440/R442 respectively.

2.1.2 Amplifiers

The Signalware AED-101 daughterboard uses the OPA685 operational amplifier to drive the inputs of the A/D converters, and the THS3001 operational amplifier to buffer the outputs of the D/A converters. The gain of the OPA685 amplifiers is set to two, by default. The input range to these amplifiers -1/2 V to +1/2 V. The gain of the THS3001 operation amplifier is set to one, by default, with equal value resistors for the feedback and input resistors. By default, the D/A amplifiers output -1 V to +1 V. See Daughterboard Descriptions for more details.

2.2 FPGA Configuration

FPGA configurations are used to adapt the FPGA to perform its function customized for the application. Tools for developing and downloading FPGA configurations are available from Xilinx. The ISE Series Software tools offer both a no cost introductory version (WebPack) and versions with more capability. The basic version will allow reconfiguration of the standard board without FPGA options. Some of the larger FPGA options can only be configured with the more advanced tools.

A test FPGA configuration is provided and loaded into the board at the factory. This configuration is described briefly in a subsection below. Top-level logic diagrams for it are in Appendix D.

2.2.1 Configuration Modes

There are two methods that can be used to configure the Spartan XL series or the Virtex-E FPGA with its logic configuration on the AED-101 daughterboard: 1) use of the serial PROM or flash configuration memory, 2) use of the Xilinx tool, iMPACT, in boundary-scan mode.

1) The nominal method of configuration on the AED-101 board is via the serial configuration memory. For this method, the FPGA must be set to the Master Serial mode with all I/O pins pulled up prior to completion of configuration. This is accomplished with resistors (R1, R2, and R3) that pull down the appropriate mode pins on the FPGA. (For the Spartan XL series, a 4.7k Ohm resistor is used to pull down only the mode pin M0 on R2; for Virtex-E, only M0 and M1 are pulled down with 0.0 Ohm resistors on R2 and R3 while M2 remains high with an internal pull-up.) In this mode, the FPGA is automatically configured from the serial configuration memory on power-up.

Either serial PROM or flash (default) configuration memory may be supplied with the board. All optional Virtex-E FPGAs are supplied with flash as follows:

1. Virtex XCV50E, or XCV100E use an XC18V01VQ44C
2. Virtex XCV200E or XCV300E use an XC18V02VQ44C
3. Virtex XCV400E or XCV600E use an XC18V04VQ44C
4. Virtex XCV1000E uses two XC18V04VQ44C

For boards with serial PROM, the making of a serial PROM is described is in a separate section below; the PROM is then inserted in the daughterboard prior to power up. For boards with flash configuration memory, the flash memory may be programmed on the board with the Xilinx tool, iMPACT. The flash configuration memory is in the JTAG chain with the FPGA. The board will have either or both of the flash configuration memory devices (U9 or U10) depending of the size of the FPGA mounted on the board.

2) The Xilinx Programmer, iMPACT (supplied with Xilinx tools), is the preferred method for configuring the FPGA with its program while debugging. The flash and the FPGA (in that order) must be configured in a chain during the setup of iMPACT. The appropriate configuration files must be selected for each device. FPGA devices use ".bit" files, and the flash devices use ".mcs" files. The ".mcs" file is made from the ".bit" file using Xilinx's Prom File Formatter. iMPACT uses the download cable (supplied by Xilinx or Insight) and the JTAG connector (J1) on the AED-101 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 1 and 2 of J1 to pull INIT low while using iMPACT to program the FPGA.

When using iMPACT to program a flash device, the jumper across pins 1 and 2 of J1 can be removed. When the board is powered up with a jumper across pins 1 and 2 of J1, the FPGA will not be loaded from the configuration memory. It will sit un-configured until loaded from iMPACT, or until the jumper is removed (LED1 will light when the FPGA is not configured). The remaining four signals (TCK, TDO, TDI, and TMS), power, and ground are also connected to the Xilinx download cable. After powering up the daughterboard, the FPGA or flash is ready to program.

When using iMPACT, it is not necessary to program both the FPGA and the flash. Load the program into the FPGA when you only want that program to exist while the power is on. When you shut the power off, the FPGA will lose its program. If you want the FPGA to be loaded with the same program the next time you turn the power on, you should load the program into the flash instead of the FPGA. The FPGA will continue to be loaded with that same program until you reprogram the flash. Refer to the section on JTAG Port for FPGA Programming for the pin-out of J1.

2.2.2 Making a Serial PROM

Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done with the PROM File Formatter, which can be accessed in the Xilinx Project Manager. This step is the same for both flash and serial PROMS. Daughterboards with a Spartan XCS20XL use an XC17S20XLPD8C serial PROM. Daughterboards with a Spartan XCS30XL use an XC17S30XLPD8C serial PROM. Daughterboards with a Spartan XCS40XL use an XC17S40XLPD8C serial PROM. Daughterboards with an XCV50E or XCV100E FPGA may use an XC1701L serial PROM, although this is not standard and some changes in jumpers are necessary.

After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.

2.2.3 FPGA Test Configuration

The test configuration provides the ability to operate the A/D converters, D/A converters, and the Digital I/O in a basic test mode. It does not provide for all possible modes, nor does it contain any digital signal processing. It is adequate to test the board and to support some applications.

In order to make the example program as flexible as possible, several control registers are provided inside the FPGA. All the registers are memory mapped and 16 bits wide. However, in 32-bit word DSP target boards with byte addressing, they are given addresses as if they were 32 bits (or 4 bytes) wide with zero for bits 0 and 1. In 16 bit word DSP target boards, these address are shifted right by two bits. In Table 2-3, both addresses are shown. Although the high order bit are shown as zero, they may have to be set to some value to address the daughterboard that depends on the DSP target board that is used. The address bits that are not connected to the FPGA (bits 15 to 6 of byte address or bits 14 to 4 of word address) are also shown as zero, but they are "don't care". The table also gives the "testing value" which is the value that the example DSP program loads into the registers for 80 MHz daughterboard clock..

Table 2-3. FPGA Control Registers

The formats for the Digital I/O registers are provided in Appendix D. In the A/D status register, bit values of "1" indicate an error conditions. Bit 0 is A/D FIFO overflow, bit 1 is A/D FIFO underflow, bit 8 is D/A FIFO overflow, and bit 0 is D/A FIFO underflow. Interrupt Start and Interrupt Period registers are 16 bit counts of A/D reads from start up to first interrupt and from one interrupt to the next. The interrupt counting is visible in the Interrupt Down Counter register. The A/D and D/A Clock Rate registers determine how many daughterboard clock cycles compose each A/D or D/A sample. The daughterboard clock is provided by the DSP target board and varies from board to board.

2.3 Mounting Daughterboard on Development Board

The AED-101 daughterboard mounts to the development board's expansion connectors with the breadboard area closest to the back panel. It is crucial that the metric standoffs provided in the mounting kit be used when mounting the daughterboard to the development board. These provide a mating height of 12.0 mm. Using anything smaller than 11.81 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the development board, it should be secured with four M3x.5x6mm metric screws through the mounting holes provided on the development board.

2.4 Running the Test Program

If the development board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off, install the development board according to the instructions provided with the development board. Test the development board. Finally, with the power off, install the daughter card.

Upon powering up the development board, the FPGA example configuration is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "ddddddd_AED101.out"where ddddddd is the designation for the EVM or DSK, can be found in the zip file for the software. For the C6201 EVM and C6701, reset the EVM board with the speed option set to 3, before starting Code Composer Studio. This sets the C6201 EVM clock speed to 160 MHz, and it sets the C6701 EVM clock speed to the fastest speed available. The speed will depend on the particular board used. For DSKs, the test program is designed to run at the factory set clock speed. The format of the output is described in Figures 2-1 and 2-2.

A voltage can be applied to J7 and J6 to see an output in this test for the standard board. The active input connectors may depend on the input option selected. Every 0.244 millivolts of input voltage will increase the average output by one binary unit. The input range into the A/D converters which gives a valid conversion result is 1.5 V to 3.5 V. At the SMB connector, this corresponds to an input of -0.5 V to +0.5 V (since the amplifier has a gain of 2, and level shifts by 2.5 V). Driving the SMB connector with less than -1.4 V or more than +1.4 V could damage the A/D converter (this would drive the A/D input with less than -0.3 V or more than +5.3 V, which is beyond the maximum limits stated in the data sheet).

Before the OK is printed at the end of the window, the program operates all of the digital I/O on J15. During the printing before the OK, only the digital I/O line 1 is on. Then each of the remaining 15 digital I/O lines is turned on one at a time for a fraction of a second. The OK is printed after the last I/O is on.

The final part of the test is the D/A test. Two sawtooth waves are produced continuously, one with positive slope and one with negative slope. These waveforms can be observed with an oscilloscope on the connector J8 and J5 shown in Table 2-2.

Figure 2-1. Display Window for AED-101 Test Program

Line| Display Window No.
----+------------------------------------------------------------
001 |*** AED 101 TEST PROGRAM STARTED ***
002 |Begin application processing (Block size = zz)
003 |Interrupts received = yy
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
013 |B= uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu
014 |[dd] www www www www www www www www www www www www www www www www
015 |[dd] www www www www www www www www www www www www www www www www
016 |[dd] www www www www www www www www www www www www www www www www
017 |[dd] www www www www www www www www www www www www www www www www
018 |Checking Digital Outputs ....
019 |OK
020 |Operating the D/A converters ....

Figure 2-2. Description of Display Window Content

Line|R/O| Explanation of Line Nos.
--- | - | Content
----+--------------------------------------------------------------
001 | R |Indicates EVM board is communicating
002 | R |Ready to start DMA and application processing
002 | - | zz = buffer size in bytes
003 | R |Indicates if data is received from daughterboard
003 | - | yy = number of frame interrupts received
004 | O |A read drop error occured in DMA processing
004 | - | ee = error code (1 = RDROP bit set;
004 | - | -1 = neither RDROP or Frame Complete set)
004 | - | pp = number of buffer last processed
004 | - | cc = DMA transfer count
005 | O |Application program requested termination
005 | - | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | - | mm = number of buffers processed by application
007 | - | rr = number of buffers recieved from DMA
008 | R |Address and block number of each block processed
-011| - | aaaa = hexidecimal value of buffer address
008 | - | bb = number of the block as received from DMA
012 | R |Averages of values from A/D in the columns of each block. The
-013| - | records contain 16 columns. The averages for the columns are in
012 | - | separate lines labeled A through P.
012 | - | uuu = unsigned average value for the block
014 | R |Samples (256) from the first buffer of data processed
-013| - | dd = index of first word in row
014 | - | www = hexidecimal value of word
018 | R |Checking digital I/O is in process
019 | R |Processing is terminated
020 | R |Output a different waveform on each D/A continuously.

R = required in display window, O = optional in display window