The AED-101 daughterboard is designed to facilitate construction of prototypes or quickly make small production runs for high speed (1-80 MHz range) sampling applications with Texas Instruments Digital Signal Processors. It fits the expansion slot of Texas Instruments Digital Signal Processing Evaluation Modules (EVM) and DSP Starter Kits (DSK) for TMS320C6xxx and C5xxx DSPs made by Texas Instruments, DNA Enterprises Inc., and Ateme. This expansion slot has both an expansion memory interface and an expansion peripheral interface which allows the daughterboard full access to all of the DSP's resources.
The AED-101 has a wide variety of applications that require high sample rates for one or two channels in and out. The inputs can be sampled at 12 bits, 70 MS/s with the ADS808Y, or 80 MS/s with the optional ADS809Y A/D converter. Each of the two A/D converters operate as one single-ended or differential channel. The A/Ds require a bias of 2.5 V on the input signals. The two THS5661A D/A converters support an output of 12 bits up to 100 MS/s with a settling time of 35 ns. The D/As have a differential current output rather than the more common single voltage output.
In order to appropriately use the inputs and outputs of the converters, the AED-101 allows mounting of both transformers for AC operation, and amplifiers for AC and DC coupled operation of the A/Ds and D/As. Each A/D and D/A may have a different option. The A/D converter input options include:
The D/A converter output options include:
Input and output filters are also available with some input and output options in single pole, two real pole or 3 pole Sallen-Key modes. Single pole filters are the default for the A/D converter with a pole well above the Nyquist frequency for noise reduction only. The D/A has no filter by default.
The advantage of this daughterboard over boards that contain only the A/D and D/A converters is that it provides breadboard space for analog signal conditioning circuits and a Field Programmable Gate Array (FPGA) for digital preprocessing before the sampled data is placed in the DSP memory. This allows prototypes with the complete front end design which is often essential to successful development in high performance applications of the DSP. The inputs to the A/D converters and the outputs from the D/A converters can connect directly to a breadboard area on which conditioning circuits can be constructed. The A/D and D/A converters have their parallel digital interface connected directly to a Xilinx FPGA which provides a flexible digital interface to the DSP.
The strategic location of the FPGA between the DSP and the converters allows it to perform many useful functions. It allows blocking and FIFO buffering of signals before they are placed in the DSP memory. This can optimize the use of DSP memory and EMIF memory bus bandwidth which is often a limiting factor in DSP applications. The FPGA can provide an input decimation filter which limits the bandwidth with sharp digital filter edges and reduces the number of samples allowing the application to work with higher initial sample rates than the DSP can handle. The FPGA can construct high speed output samples for the D/A converters based on DSP inputs or the signal coming from the A/D converters. The FPGA also connects to the external digital I/O connector and to the clock/control lines of the converters. This allows synchronization of the converters with either external signals or with DSP signals.
Although the FPGA configuration supplied with the board for testing can be used as-is in some cases, in general some reconfiguration of the FPGA is necessary to adapt the board to particular applications. An FPGA configuration that provides decimation is necessary to provide for the highest sampling rates because in most cases the DSP's EMIF bus will not handle the full output of the AED-101 which is up to 80 M words per second of 32-bit words.
The breadboard area consists of 3 sq. in. of 50 mil pitch surface mount or DIP component area. This allows a wide variety of components to be wired into signal conditioning circuits. The breadboard area is served by separate + and - regulated power supplies for sensitive analog components. Up to eight SMB coax connectors for analog signals are adjacent to the breadboard at the edge of the daughterboard. By default the board comes with 4 SMB connectors and an empty breadboard area.
Modifications/additions to the amplifier configuration and the breadboard are easily accomplished with a temperature controlled solder iron and a pair of hot tweezers. The 0603 surface mount components can be mounted/dismounted without additional special equipment. A magnifying lens or low power microscope are also use for inspection.
SIGNALWARE provides technical support for all aspects of the use of the AED-101 including signal conditioning circuit design, FPGA configuration programming, and DSP software programming. SIGNALWARE can provide a turnkey solution for prototyping a DSP application. Signal conditioning circuits can be mounted and wired on the board at the time of manufacture at less cost than having a technician or engineer wire them on the board afterward. SIGNALWARE also provides a 90 day limited warranty against workmanship and component defects.