3. DAUGHTERBOARD DESCRIPTION

3.1 Block Diagram

The block diagram in Figure 3-1 shows the major hardware components including optional flash with a hypothetical FPGA program the demonstrates use of all these components.

In the following subsections, reference to this block diagram and the schematics in Appendix A are made.

3.2 FPGA Functions

The FPGA is referenced as U1 on the daughterboard. All of the signals in the EVM external interfaces feed into the FPGA. The FPGA is also connected to the control lines on the flash, and all of the digital lines of the converters and phase-locked loop.

Not shown in Figure 3-1 are the 8 digital I/O. These connect from the FPGA to a 74ABT244 buffer (U11), and then to a 10-pin connector (J2).

The FPGA controls the interface between the EVM board and the daughterboard. All signal traffic goes through the FPGA except for the address and data lines driving the flash. Only the control lines on the flash are wired to the FPGA. The FPGA can use the address lines from the EVM to decode reads/writes to the flash, to the digital I/O, and to the converters.

On power-up, the FPGA is automatically loaded from the serial PROM (U2). The FPGA program can then direct the flash to boot-load the DSP. This operation is covered in more detail in the software section of the manual.

Another useful function is preprocessing of the A/D samples before sending them to the DSP. This can greatly reduce the load on the DSP. Processor load can also be reduced by using the DMA to retrieve the samples from the FPGA and writing them directly to memory. The FPGA can control EXT_INT7 and read the DMA control which facilitates the DMA interface. An example of this can be seen in the sample program.

In addition, all of the lines for the DSP serial ports, DSP clocks, DMA control lines and the control/status lines from the EVM are available at the FPGA pins.

3.3 A/D Converters and Input Amplifiers

The A/D converters, TLC5540, are referenced as U5 and U6 in the schematics. The input amplifiers, THS3001, are referenced as U3 and U4. The input analog signal can be applied to pin 2 of R10 or R11. This drives the positive input of the op-amp (pin 3). If the input resistors are not used, the input signal can be tied into the open hole which connects to pin 3 of the op-amp.

To adjust the gain of U3, the resistance of R8 and/or R19 can be changed. Similarly, to adjust the gain of U4, the resistance of R14 and/or R20 can be changed. Refer to the THS3001 data sheet for suggested resistors values.

The control signals for the A/D converters are the clock and output enable. These are driven by the FPGA. For both A/D converters, the top end reference voltage is set to 2.63 V, and the bottom end reference voltage is set to 0.61V. For information on adjusting the A/D reference voltages, refer to the TLC5540 data sheet.

3.4 D/A Converters and Output Amplifiers

The D/A converters, TLC7524, are referenced as U9 and U10 in the schematics. The output amplifiers, THS4001, are referenced as U7 and U8. The FPGA controls the operation of the D/A converter. By driving the WR pin on the D/A converter, data is clocked into the converter.

The outputs of the amplifiers are wired to holes near the breadboard area. These holes are labeled as B2 and B4.

3.5 Phase-Locked Loop

The phase-locked loop, TLC2933, is referenced as U12 on the schematic. The FPGA controls the entire chip. The inhibit line from the FPGA drives both the PFD inhibit and the VCO inhibit on the TLC2933. For a x1 output from the VCO, pull the TEST line low. For a x ½ output, pull the TEST line high. The locking frequency range is from 43 MHz to 100 MHz (x1 output).

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase difference between two frequency inputs supplied to FIN-A and FIN-B. Nominally the reference is supplied to FIN-A, and the frequency from the external counter (implemented in the FPGA) is fed to FIN-B. The PFD output is filtered before it is fed to the VCO input. The output of the VCO is wired into the FPGA. For more information on the operation and filtering, refer to subsection 2.1.1 and the TLC2933 data sheet.

3.6 Digital Buffers

The digital buffer chip, U11, is a 74ABT244. It buffers the digital signals between the FPGA and the connector J2. It can support digital I/O up to 100 MHz. The buffer is always enabled.

3.7 Flash Memory (optional)

The flash memory chips, AM29F400B, are referenced as U13 and U14. These do not come standard on the board, but can be purchased as options. These are each 4.0 Megabit, CMOS 5.0 Volt-only boot sector flash memory. They can be written to directly with the DSP. The FPGA is used to insert wait states into the read/write cycles. The flash can be used to boot-load the DSP on power-up. The example program provided does not provide for the interface to the Flash memory. This function can be programmed into the FPGA by the user. Refer to the AM29F400B data sheet for details on operation.

3.8 Breadboard Area

The breadboard area was designed for building custom analog circuitry. There are locations for six SMB connectors beside the breadboard area. These can be used for the analog I/O. Also neighboring the breadboard area are the input and output amplifiers for the converters. The breadboard area was designed for using both through-hole and 50 mil surface-mount components. The breadboard has +/- 8 Volts available throughout. See the layout of the breadboard for the locations of power and ground connections.

3.9 Interfaces

3.9.1 EVM Expansion Connectors

Two 80 pin connectors provide the interface between the EVM and the daughterboard. One expansion connector provides access to the DSP's asynchronous EMIF, and the other provides access to the DSP's peripherals and control/status signals. Both connectors also provide power to the daughterboard. Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the EVM board.⁽¹⁾

The expansion memory interface connector has a reference designator of J6 on the EVM and J9 on the daughterboard. The expansion peripheral interface connector is J7 on the EVM and J10 on the daughterboard. The pinouts are in Tables 3-1 and 3-2 respectively below. The connection inside the daughterboard is listed. Of particular interest is the FPGA pin number which must be referenced in FPGA configurations in order the make the proper connections in the FPGA.

Table 3-1. Expansion Memory Interface

Table 3-2. Expansion Peripheral Interface Connector

3.9.2 JTAG Port for FPGA Programming

The JTAG connector is a 14-pin double-row header that has a reference designator of J1 on the daughterboard. When using the JTAG Programmer to load the FPGA configurations, the INIT pin on the FPGA must be pulled low. This is accomplished by placing a jumper between pins 2 and 4 on J1. The pin-out for J1 is shown in Table 3-3. The connection to the PC is intended to be made with the Xilinx download cable.

3.9.3 Digital I/O Connector

The Digital I/O Connector has a reference designator of J2 on the daughterboard. This is a 10-pin double-row connector. This connector has 4 inputs, 4 outputs, and 2 grounds. The buffering between the FPGA and J2 is done with a 74ABT244. The pin-out for the connector is shown in Table 3-4 with the FPGA pin which corresponds with the connector pin.

3.9.4 Analog I/O Connectors

The AED-100 daughterboard has positions for 6 SMB connectors. Their reference designators are J3-J8. The connectors are not hard-wired to anything except a test point. A hand wire can be placed from the test point to the desired analog signal. Two of these connectors (J5 and J7) are provided with the board. You can also purchase and mount additional connectors if desired. The board was designed to use a narrow SMB connector supplied by Digi-Key, part number J470.

1. TMS320C601/6701 Evaluation Module Technical Reference, (literature number SPRU305), Texas Instruments, 1998.