2. CONFIGURATION AND INSTALLATION

2.1 User Selected Components

The Signalware AED-100 daughterboard was designed with flexibility in mind. Besides the breadboard area, there are several components which are user selectable. Most of these components are through-hole for ease of use, but due to wire length restrictions, some components must be surface mount. The schematics make clear which user selectable components are surface mount.

2.1.1 Phase-Locked Loop

The Signalware AED-100 daughterboard uses a TLC2933 high-performance phase-locked loop (PLL) for clock generation. The PLL interfaces through the FPGA, and can be used to generate a wide range of frequencies. For example, the EVM board provides the FPGA with either a 66.5 MHz or 80 MHz clock. The FPGA can divide that clock by any integer before sending it to the PLL. The PLL can then multiply that clock by any integer (within the PLL specification) before sending it back to the FPGA. The FPGA can again divide that clock by any integer to reach the desired frequency before supplying it to the D/A or A/D converters.

A lag-lead low-pass-filter is used to filter the VCO input to the PLL. There are two resistors (R16 and R17) and two capacitors (C66 and C67) that make up the filter, which are user selectable. See Table 2-1 for the default component values. Refer to the TLC2933 data sheet for information on tuning the low-pass-filter; Table gives the relation between the board component identification and the component identification in the data sheet. The data sheets for all Texas Instruments components can be downloaded from the TI web site (http://www.ti.com).

2.1.2 Amplifiers

The Signalware AED-100 daughterboard uses THS3001 high-speed current-feedback amplifiers to drive the inputs of the A/D converters. The gain of these amplifiers can be adjusted by the user by changing either R8 or R19 for U3, or R14 or R20 for U4. The data sheet lists the recommended values for various gains. The board is initially built with 750 Ohm resistors which gives a gain of 2. The input signal should be applied to the leg of R10 for U3 and R11 for U4. R10 and R11 may be removed to increase input impedance if appropriate bias is applied to the amplifier inputs.

2.2 FPGA Programming

Tools for developing and downloading FPGA programs are available from Xilinx. The Foundation series of tools offers both a low cost introductory version (basic) and a full capability version. The basic version will program the standard board without FPGA options

2.2.1 Configuration Modes

There are two methods that can be used to program the Xilinx 4000XL series FPGA on the AED-100 daughterboard: use of the serial PROM or with the J-TAG Programmer.

The default method of configuration on the AED-100 board is via the serial PROM. For this method, the FPGA must be set to the master serial mode. This is accomplished with the 4.7k Ohm resistors (R1, R2, and R3) that pull the mode pins on the FPGA low. In this mode, the FPGA is automatically configured from the serial PROM on power-up. This method is good for a final program, but is not convenient when debugging programs.

The J-TAG Programmer (supplied by Xilinx) is the preferred method for downloading programs to the FPGA while debugging. The J-TAG Programmer uses the download cable (also supplied by Xilinx) and the J-TAG connector (J1) on the AED-100 board. The mode of the FPGA can be left in master serial or be put in any other mode, however, a jumper must be placed across pins 2 and 4 of J1 to pull INIT low. The remaining four signals, power, and ground can then be connected to the Xilinx download cable, and the FPGA is ready to program. Refer to Section 3.9.2 for the pin-out of J1.

2.2.2 Making a Serial PROM

Once a final program is ready to be placed in a serial PROM, a PROM file must be made. This is done in the Xilinx Project Manager. Daughterboards with an XC4010XL, XC4013XL, or XC4020XL FPGA use an XC17512L serial PROM. Daughterboards with an XC4044XL FPGA use an XC1701L serial PROM.

After a PROM file has been generated, use a PROM programmer (not supplied by Signalware) to load the PROM file into the serial PROM. Be sure to set the reset option to active low. This can be done before or after programming the PROM. Now the serial PROM is ready to be inserted into the socket (U2) on the daughterboard. The Xilinx web site (support.xilinx.com) has a list of programmers that will program these PROMs.

2.3 Mounting Daughterboard on EVM

The AED-100 daughterboard mounts to the EVM's expansion connectors with the bread board area closest to the back panel. It is crucial that the standoffs provided be used when mounting the daughterboard to the EVM board. These provide a mating height of 11.9 mm. Using anything smaller than 11.81 mm (mating height of the connectors) could damage the board. Once the daughterboard has been mounted on the EVM board, it should be secured with four metric screws through the mounting holes provided on the EVM board.

2.4 Running Test Program

If the EVM board has not been previously installed, install the drivers and the Code Composer Studio software. Then with the power off install the EVM and daughtercard.

Upon powering up the EVM board, the FPGA sample program is automatically loaded and running. To test the daughterboard, run the DSP test program and examine the results. This program, "aed100r1.out", can be found on the provided floppy disk. Before loading the program, reset the EVM board with the speed option set to 3. This sets the EVM clock speed to 160 MHz. Now load and run the program using Code Composer Studio. The format of the output is described below.

Description of the Display Window for AED-100 Test Program

Line| Display Window
No. | Content
----+------------------------------------------------------------

001 |*** AED TEST PROGRAM STARTED ***
002 |Buffer Allocation Error [ssXyy]
003 |Begin application processing (Buffer size = zz)
004 |Read drop error ee (bufct=pp, trnct=cc)
005 |Application Termination tt
006 |FPGA FIFO Overflowed
007 |Test Loops = ll Bufs Processed = mm Bufs Received = rr
008 |Block Addresses aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
009 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
010 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
011 | aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb) aaaa(bb)
012 |A= uu uu uu uu uu uu uu uu uu uu
013 |B= vv vv vv vv vv vv vv vv vv vv
014 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
015 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
016 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
017 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
018 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
019 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
020 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
021 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
022 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
023 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
024 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
025 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
026 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
027 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
028 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
029 |[dd] wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx wwxxwwxx
030 |OK

Line|R/O| Explanation of Line
Nos.| / | Content
----+---+--------------------------------------------------------------

001 | R |Indicates EVM board is communicating
002 | O |Buffers could not be allocated in heap (terminates program)
002 | R | ss = size of each buffer in bytes
002 | R | yy = number of buffers required
003 | R |Ready to start DMA and application processing
003 | R | zz = buffer size in bytes
004 | O |A "read drop error" occured in DMA processing
004 | O | ee = error code (1 = RDROP bit set;
004 | O | -1 = neither RDROP or Frame Complete set)
004 | O | pp = number of buffer last processed
004 | O | cc = DMA transfer count
005 | R |Application program requested termination
005 | R | tt = termination code from application program
006 | O |Data storage FIFO in FPGA overflowed
007 | R |Summary information collected in processing
007 | R | ll = number of times buffer ready tested
007 | R | mm = number of buffers processed by application
007 | R | rr = number of buffers recieved from DMA
008-| R |Address and block number of each block processed
011| R | aaaa = hexidecimal value of buffer address
008 | R | bb = number of the block as received from DMA
012 | R |Averages of values from A/D "A"
012 | R | uu = unsigned value
013 | R |Averages of values from A/D "B"
013 | R | vv = unsigned value
014-| R |Samples (128) from the first buffer of data processed
029| R | dd = index of first word in row
014 | R | ww = hexidecimal value of samples from A/D A
014 | R | xx = hexidecimal value of samples from A/D B
030 | R |Processing is teminated

R = required in display window, O = optional in display window

You can apply a signal to pin3 of U3 and U4 to see an output in this test. Every other A/D sample is from each A/D converter. With the default gain setting on the A/D input amplifiers, every 4mV of input voltage will increase the output by one hex value. This results in an input voltage range to the amplifiers of 0.3V to 1.3V. The output of the amplifiers driving the A/D converters should be no less than -0.3 Volts and no greater than 5.3 Volts. This corresponds to an input voltage of -0.15V to 2.65V. Exceeding this range could damage the converters.