TMS320 C5416 DSP Development Board compatibility with Signalware Daughterboards

Mechanical Fit

The TMS320 C5416 DSK is constructed (based on beta model) with components in the restricted keep-out areas documented in SPRA711 which are too high.

On the AED-100 board, these components conflict with the SPROM used to configure the FPGA. Therefore, the board could only be used with the SPROM removed, and the FPGA would have to be configured with Xilinx software tools each time the DSK was powered up or with an off-board configuration module (special order).

On the AED-109, 3xx and other new daughterboards, some daughterboard I/O SMB connectors, when mounted on the component side of boards, conflict with the DSK components. Moving selected connectors to the other side of the daughterboard solves this problem.

These problems are addressed by ordering the special mechanical C5416 adaptation option on the daughter board . The option number is 1m5416; the cost is $25 USD.

This option makes the following changes to the board:

The JTAG FPGA configuration connector is mounted on the reverse side.
The SPROM and socket are removed (AED-100 only).
The SMB input/output connectors are mounted on the reverse side.

These changes to the daughterboard do not prevent the card being used with other development boards; however, the single slot clearance with PCI Development cards is not maintained.

There can also be special considerations with stacking multiple daughterboards. Contact Signalware for special ordering information if multiple stacked daughterboards are required with the 5416 DSK.

Sampling Rate Restriction

The C5416 has a limitation on the rate at which it can import data on the EMIF bus. The bus is 16 bits wide and capable of more than 11 Mwords/second (beta test DSK model) The alternative solutions include:

The daughterboard sample clock rate can be slowed down to fit within the limitations of the DSK EMIF bus. Based on a 160 MHz CPU clock rate, 80/n MS/sec (where n is an integer) are available for sample rates. For example, if 2 12-bit A/D converters were used on the bus (no D/As), each could operate at 5 MS/s (n=16) and remain within the board limitation.
The A/D sample maximum available clock rate can be maintained and a subset of the samples can be sent to the DSP. This maintains the low latency of a fast A/D without overloading the EMIF bus. This solutions is useful in feedback control applications.
Custom algorithms may be placed in the FPGA on the daughterboard which filter, decimate, detect or otherwise process the A/D or D/A samples to keep the throughput within the limits of the EMIF bus.

The first two solutions may be implemented with appropriate register setting in the daughterboard. (New ISE based FPGA configurations may be necessary to do this in some cases; check on availability by contacting Signalware.) By default, the daughterboard test program will employ the second solution above. The third solution requires changing the FPGA configuration to operate within the limitations of the C5416 DSK board. In order to change the FPGA configuration on the daughterboard, two approaches may be used:

Signalware can provide custom FPGA configurations to meet customer requirements. Request a quotation with your specifications for sample processing. The daughterboard is delivered with the custom configuration loaded and tested. Signalware recommends obtaining an FPGA JTAG download cable (separately ordered accessory) in order to maintain the board at the customer site.
The customer may modify the FPGA configuration after the board is received. The customer will need Xilinx software tools to design the FPGA configuration. For daughterboards with a Virtex E option, software is available free of charge on the Xilinx web site. This software has limited capability. Other software packages are available from Signalware and through Xilinx distributors. An FPGA JTAG download cable will also be required.

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For information on the Signalware daughterboards, see our Summary of Signalware Daughterboards.

See SIGNALWARE's Home Page or Customer Reply Form for further assistance.