AED-xxx Expansion Daughterboard Interface

TMS320C6x EVALUATION MODULE

Analog Expansion Daughterboard

AED-xxx Expansion Interface

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9/5/00

The following is a description of the interface between the SIGNALWARE AED line of daughter cards and the parent card via the two 80 pin connectors. The connectors are refered to as MEM_IF for the "Expansion Memory Interface Connector" and IO_IF for the "Expansion Peripheral Interface Connector". The listing is organized by type of connection.

Ground connections --

MEM_IF pins 11, 12, 31, 32, 51, 52, 61, 62, 71, 72, 79, 80

IO_IF pins 3, 4, 7, 8, 25, 26, 31, 32, 37, 38, 43, 44, 51, 52,

61, 62, 75 (Note 1), 76, 77, 79, 80

+5 Volt connections --

MEM_IF pins 1, 2, 21, 22

IO_IF pins 5, 6, 9, 10

+3.3 Volt connections --

MEM_IF pins 41, 42

IO_IF pins 19, 20

12 Volt connections (Note 2) --

IO_IF pins 1(+), 2(-)

FPGA I/O pin connections (Note 3) --

MEM_IF pins 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 27, 28,

29, 30, 33, 34, 35, 36, 37, 38, 39, 40, 43, 44, 45, 46,

47, 48, 49, 50, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64,

65, 66, 67, 68, 69, 70, 73, 74, 75

IO_IF pins 22, 23, 24, 27, 29, 30, 33, 34, 35, 36, 39, 41, 42,

46, 49, 50, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 65,

66, 69, 70, 71, 72, 73, 74

FPGA clock pin connections (Note 4) --

IO_IF pins 21, 45, 78 (Note 5)

Ready signal connection (Note 6) --

MEM_IF pin 76

Spare pin connection (Note 7) --

MEM_IF pin 17, 18, 19, 20, 23, 24, 25, 26, 77

IO_IF pin 11, 12, 13, 14, 15, 16, 17, 18, 28, 40, 47, 48, 67, 68

Notes:

1) This pin is grounded on the daughterboard. It may be used as a daughterboard connect signal on the main board.

2) The +/- 12 Volt supply may alternately be connected directly to J2 on the daughterboard on the AED-103, 106, and 200. The +/- 12 Volts is used only to power the +/- analog supplies for the analog signal amplifiers. 3) An FPGA I/O pin may be set to operate as either a input, output or high-Z by the FPGA configuration. Prior to configuration of the FPGA these pins are high-Z.

4) An FPGA clock pin is connected to a global clock line in the FPGA which may be used for clocking the logic. For Virtex FPGAs, these pins are input only. For 4000 and Spartan FPGAs, these pins are I/O pins as well as clock and may be used either way.

5) Pin 78 is normally the DSP external clock. This pin has a 820 ohm pulldown resistor to provide loading to get clean clock edges.

6) The ready signal is connected so that it receives a low before FPGA configuration is complete. This prevents the DSP from accessing the memory bus until the FPGA is configured. This feature is necessary to use the boot load from flash on the daughter

card. After configuration, the ready signal is high unless the FPGA configuration controls this pin. For the Virtex FPGAs, it is supplied by an inverter driven from an FPGA IO pin. For the 4000 and Spartan FPGAs, it is supplied by the LDC (Low During Configuration) pin, On the AED-103 (Rev. 1), AED-106, and AED-200 daughter boards a 4.7k pullup has been provided to 3.3 Volts to insure that it is high after configuration. Some main boards also provide a pullup on this line, so that the AED-100, AED-102 and AED-103 (Rev. 0) also function correctly. However, where neither board provides a pullup, one must be added to provide correct functionality.

7) Spare pins are not used in the standard connection of the interface. However, on some main boards these pins are used. In some cases, it may be necessary to connect to the pins. Holes are provided to connect wires from the spare pins to other FPGA pins that may not be used on a particular main boards on the AED-103, 106 and 200.