APPENDIX E. TEST SOFTWARE STRUCTURE DIAGRAMS
The example program FPGA logic schematics are on the following pages and shown in the table below:
| Sheet | Description | Module |
| Page 1 | Main Program Structure | AED_MAIN |
| Page 2 | Error Processing Structure | AED_MAIN |
| Page 3a | Data Movement Services Structure-Part A | AED_DMS_CPU |
| Page 3b | Data Movement Services Structure-Part B | AED_DMS_DMA |
| Page 4 | Application Program Structure | AED_appl |
The structure diagrams show how the functions in each module use the functions in other subordinate modules of the test program. At the top of each diagram, the calling module is shown as a dashed-line box with the some or all of its functions represented by solid-line boxes within. In the low part of the diagram, the subordinate functions employed by the functions of the calling module are shown as solid-line boxes. These boxes are enclosed by dashed-line boxes showing the subordinate modules that contains the functions represented by these boxes. Lines from the calling functions go to all the called functions below.
Overall these diagrams show higher levels of the calling tree of the test program. Diagrams are included for only the modules which call functions in other modules. BRD_HDR represents the interface to the board support module. This module is EVM/DSK board dependent. Its calling tree is not show and depends on the board supported. The board support module functions call functions in libraries provided for each board by the vendor.
