APPENDIX D. EXAMPLE FPGA PROGRAM SCHEMATIC
The test configuration FPGA logic schematics are shown in the table below:
| Sheet | Description |
| AED_VHDL_Top | Top Level Structure (1xx, 2xx and 3xx) |
| Input/Output Data Register and Control | |
| Digital I/O Control | |
| AED_VHDL_CLK | Clock Selection |
| AED_VHDL_Buf | Data Queue |
| AED_VHDL_INTR | Generate Interrupts |
| AED_VHDL_ADC | Mixed Signal Control Skeleton |
| Top Level Structure (AED-200/300 only) | |
| Generate Test Data (AED-200/300 only) |
