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The SIGNALWARE AED-300 Fine Pitch Flex Analog Expansion Daughterboard for the Texas Instruments TMS320C5x/6x Evaluation Module and Starter Kits provides an economical way of building a custom analog interface for the DSP. The AED-300 has a 168-pin surface mount pad mixed-signal area that can accommodate several .65 mm (25 mil) pin spacing A/D and D/A converter packages. The configuration table (below) contains suggested numbers and types of TI and Burr Brown devices that can be mounted. Many other devices can be mounted as well if they have the .65 mm pin spacing and the SSOP, TSSOP or MSOP packaging. An FPGA provides a programmable interface from the converters to the DSP and 16 buffered digital I/O signals. An amplifier area provides for 6 analog channels. In addition, the AED-300 provides breadboard space for building signal conditioning and interface circuits. This board supports applications with signal bandwidths into the 10's of MHz.

The standard AED-300 consists of a daughterboard for the expansion interface on the C5x/6x Evaluation Module or Starter Kit. The full size TI standard daughterboard includes voltage reference, digital buffers, configurable logic interface to DSP (FPGA), and a 40 pin double row 50 mil I/O connector. Space is provided for mounting regulators, a 20 pin double row 50 mil I/O connector and 4 SMB coax connectors. The AED-300 comes with a manual, a demonstration FPGA logic configuration and test program for the DSP.

SIGNALWARE provides mounting services to convert the AED-300 into a custom prototype analog interface for a DSP based system. A/D and D/A converters along with option filters and amplifiers are mounted as the board is assembled ensuring reliable soldering of surface mount components. SIGNALWARE also can provide custom FPGA logic configurations and DSP application programs for turnkey use of the product.

Configurable DSP I/F Adds Performance

Preprocessing of the A/D samples and control of the mounted devices with the Field Programmable Gate Array (FPGA) significantly reduces the load on the DSP making more computation possible with a single DSP. A Xilinx Spartan^TM XCS20XL FPGA with 20,000 logic gates (1120 flip-flops, 12K RAM bits) is standard, and larger FPGAs are available as options. Serial flash memory, socketed PROM or the JTAG port provide support for FPGA configuration.

Digital I/OAdds Convenience

On the standard board, 16 bits of digital inputs or outputs are provided with LVTTL compatible buffers. The default configuration is 4 inputs, 4 outputs and 8 bidirectional I/O that may be dynamically switched in direction. Optionally, two sets of 8 bidirectional I/O may be provided instead. These I/O appear on the 40 pin connector. The digital I/O are controlled by two 16 bit memory mapped registers implemented in the FPGA.

More digital I/O can be provided by mounting additional buffers or transceivers in the mixed signal area. The 40 pin connector is designed to provide for a total of 32 digital I/O.

Additional Component Space Adds Flexibility

To make the analog interface to the board convenient and flexible, 4 transformer mounts, 2 single buffer amplifiers, 2 dual buffer amplifiers and 3 sq. in. of multipurpose breadboard space for mounting devices with up to 72 pins are provided. The analog interface to the converters always needs to be tailored to the application. No approach is more flexible than a breadboard area specifically designed for surface mount and through-hole analog ICs. The AED-300 breadboard accommodates wide and narrow SOICs (50 mil pitch) as well as 0.3 and 0.6 DIPs (100 mil pitch). By keeping the signal conditioning circuits on the board with the converters, noise, errors, and cost are reduced. All buffer amplifiers have flexible configurations with inputs adjacent to the breadboard area. Regulated +/- DC analog power buses supply the breadboard area.

The AED-300 may have 512 Kbyte or 1 Mbyte optional flash memory for DSP program and data storage for use on main boards without any or adequate flash memory.

The AED-300 has a stacking connector option that allows it to be used with other daughterboards to assemble more complex prototypes.

Configuration Tables

The tables below give some predefined configurations of mixed-signal parts that can coexist in the mounting area of one board. Many other configurations of these and other A/D, D/A and CODEC devices are also possible.

Many other types of devices, e.g. RS422/485 transceiver, can be mounted in the mixed signal area beside those in the tables. The devices must have SSOP, TSSOP or MSOP packages, a total of 160 pins or less, and 56 digital connections to the FPGA or less. Pins may also be connected to grounds, power supplies, reference voltages, off board connectors and various analog circuits. Most connections are made with 0603 surface mount components; few wires are required.

Audio CODEC Boards (AED30x Series)

All of the daughterboards in the table below use stereo, audio CODECs including 2 A/Ds and 2 D/As each:

CODEC devices suggested for AED-30x Series Daughterboards:

Click on the device part numbers to see the manufacturers data sheet for the device. Due to the flexible nature of this board, the devices may not perform exactly as specified in the data sheets. However, the data sheet gives the maximum performance that may be expected and generally actual performance is near the specified levels. These devices are in addition to any CODEC that may mounted on the target DSP board.

The standard FPGA configuration for the AED-30x series boards is: The CODECs are controlled by one McBSP serial port on the DSP. This allows the device configuration registers to be set from DSP software. The control of the device afforded by these registers is quite extensive including gains and filtering. The data is received from and transmitted to the devices by 32-bit memory mapped registers using the EMIF port on the DSP. The registers may be either a 16 bit 2 channel packed format or a 24 bit unpacked format. Use of DMAs in the DSP to handle this data transfer is recommended. The CODEC clock speed is set by an oscillator mounted on the daughterboard. The default value is 48 MHz which is divided by 4 for the CODEC clock (12 MHz).

12 Bit Boards (AED32x Series)

All of the daughterboards in the table below use single channel, parallel A/Ds and D/As:

All of the daughterboards in the table below use single channel, parallel A/Ds and serial D/As with 1 or 2 channels each:

12- bit A/D devices suggested for AED-32x Series Daughterboards:

12- bit D/A devices suggested for AED-32x Series Daughterboards:

Click on the device part numbers to see the manufacturers data sheet for the device. Due to the flexible nature of this board, the devices may not perform exactly as specified in the data sheets. However, the data sheet gives the maximum performance that may be expected and generally actual performance is near the specified levels.

The standard FPGA configuration for the AED-32x series boards is: The sample rates for the A/Ds and D/As are controlled by two memory mapped registers. These registers control the number of daughterboard clock cycles that comprise a A/D or D/A sample respectively. This allows the sampling rate to be set to submultiples of the clock from DSP software. Some devices only operate with even submultiples because they require symetric sample clocks. The data is received from and transmitted to the devices by memory mapped 12-bit FIFOs using the EMIF port on the DSP. The format of the data is 32-bit with 2 channels of 12 bit data packed into two 16 bit fields. Use of DMAs in the DSP to handle this data transfer is recommended. The daughter board clock speed is set by the EMIF clock speed used on the target DSP board.

Optionally, an oscillator may be mounted on the daughterboard to provide an independent daughterboard clock. This allows a much wider selection of A/D and D/A sample rates. If sychronization of the A/D and D/A sample times with external hardware is required, an external oscillator may be connected through a digital I/O input to supply the clock. In either case, the oscillator frequency must be between 25 and 80 MHz, and a Virtex FPGA option must be used to accommodate the mixed clock operation.

16 Bit Boards (AED35x Series)

All of the daughterboards in the table below use 4 channel, serial A/Ds and 1, 2 or 4 channel, serial D/As:

16- bit A/D devices suggested for AED-35x Series Daughterboards:

16- bit D/A devices suggested for AED-35x Series Daughterboards:

Click on the device part numbers to see the manufacturers data sheet for the device. Due to the flexible nature of this board, the devices may not perform exactly as specified in the data sheets. However, the data sheet gives the maximum performance that may be expected and generally actual performance is near the specified levels.

The standard FPGA configuration for the AED-35x series boards is: The clock speed, sample rate, channel selection and other flexible parameters for the A/Ds, if any, are controlled by one McBSP serial port on the DSP. Similarly, the D/As, if any are controlled by another McBSP serial port. This allows these device configurations to be set from DSP software. The data is received from and transmitted to the devices by 32-bit memory mapped registers using the EMIF port on the DSP. The register format is two 16 bit fields packed into a 32-bit word. Use of DMAs in the DSP to handle this data transfer is recommended. Optionally, a daughterboard mounted or external oscillator can be used to obtain particular sample rates or synchronization. Optional RAM control of the A/Ds and/or D/As can be configured in the FPGA so that the McBSP(s) are freed up for other uses.

24 Bit Boards (AED38x Series)

All of the daughterboards in the table below use 4 or 8 channel, serial A/Ds and 2 or 6 channel, serial D/As:

24- bit A/D devices suggested for AED-38x Series Daughterboards:

24 - bit D/A devices suggested for AED-38x Series Daughterboards:

Click on the device part numbers to see the manufacturers data sheet for the device. Due to the flexible nature of this board, the devices may not perform exactly as specified in the data sheets. However, the data sheet gives the maximum performance that may be expected and generally actual performance is near the specified levels.

The standard FPGA configuration for the AED-38x series boards is similar to the AED-35x series described above except that the data is not packed. The data registers are 32-bit memory mapped with one 24 bit field in them.

AED-300 Specifications

Digital Interface to EVM/DSK:

• Xilinx Spartan^TM or Virtex-E^TM FPGA.
• Full speed interface with EVM memory, serial ports, interrupts, DMA, and clocks.

Debugging Interfaces:

• JTAG - 14 pin FPGA and configuration flash memory

Digital I/O and External Synchronization:

• 16 - Buffered TTL Input/Outputs up to 100 MHz
• Standard - 4 inputs, 4 outputs, and one group of 8 switchable to input or output.
• Option 1t - Two groups of 8 switchable to input or output.

Operating Temperature Range: 0 to 40 degrees C

Power: +5, +3.3, +/-12 VDC

Size: 191 mm L x 86.2 mm W x 13.8 mm D

Net Weight: 0.14 (0.31) kg ( lb.)

Ordering Information

AED-300 Analog Expansion Daughterboard

Opt. 1a - 512 Kbyte Boot Flash Memory

Opt. 1b - 1.0 Mbyte Boot Flash Memory

Opt. 1c - Stacking Interface Connectors**

Opt. 1d - High Power 1.8V Supply**

Opt. 1o - xx.xx MHz External Oscillator (25 to 80 MHz)

Opt. 1t - Digital I/O 2x8 Bi Transceivers Only

Opt. 2g-6/8 - XCV50E-6/8* FPGA Substitution

Opt. 2a-6/8 - XCV100E-6/8* FPGA Substitution

Opt. 2c-6/8 - XCV200E-6/8* FPGA Substitution

Opt. 2d-6/8 - XCV300E-6/8* FPGA Substitution

Opt. 2e-6/8 - XCV400E-6/8 FPGA Substitution

Opt. 2f-6/8 - XCV600E-6/8 FPGA Substitution

Opt. 2h-6/8 - XCV1000E-6/8 FPGA Substitution

Opt. 2t - XCS30XL-4 FPGA Substitution

Opt. 2u - XCS40XL-4 FPGA Substitution

Opt. 3a - A/D - D/A Custom Mixed Signal Mounting - charge per Required Position

Opt. 3b - Buffer Amplifier - charge per Channel

Opt. 3f - Custom Analog Filters

Opt. 4a - A/D FPGA Test Configuration - charge per Device used on board(s)

Opt. 4b - D/A FPGA Test Configuration -charge per Device used on board(s)

Opt. 4 - Custom FPGA Configuration

* Free configuration tools available from Xilinx (WebPack). Other FPGAs require purchased tools.

** Stacking Interface Connectors and High Power 1.8V Supply options are mutually exclusive.  Stacking connectors are required when more than one board is used on a single DSK or EVM.  The High Power may be mounted on the outer most daughterboard, and it may supply FPGAs on more than one daughterboard.  High Power 1.8V Supplies are recommended for all FPGA options XCV300E-8 and above.

Pricing and Delivery:Please complete a Request of Quotation form. Your request will be processed for direct purchase from Signalware or forwarded to the appropriate distributor.

Terms and Conditions: Contact distributor except for direct purchase.

For information on other daughterboards, see our Summary of Signalware Daughterboards.

For information on DSP Development boards that use Signalware daughterboards, see our Summary of DSP Development Products.

For information on various combinations of TMS320C5x/C6x EVM and DSK products listed above with the Signalware daughterboards, see our Prototype Configuration Table.

See SIGNALWARE's Home Page or Customer Reply Form for further assistance.