TMS320C5x/C6x EVALUATION MODULE

Analog Expansion Daughterboard

AED-200 (Multi-Purpose Medium Speed)

See SIGNALWARE's Home Page or Customer Reply Form for further assistance.

AED-200 Multi-Purpose Medium Speed Daughterboard

DATA SHEET

The SIGNALWARE AED-200 Multi-Purpose Analog Expansion Daughterboard for the Texas Instruments TMS320C5x/C6x Evaluation Module provides an economical way of building a custom analog interface. The AED-200 has an 84-pin surface mount pad area that can accommodate several 50 mil pin spacing A/D and D/A converter packages. See the configuration tables to determine the number and type of devices that can be mounted. An FPGA provides a programmable interface from the converters to the DSP and three groups of 8 buffered digital I/O signals that can be either input or output. In addition to the mixed signal mounting area, breadboard space is provided for building signal conditioning and interface circuits. This board has application with signal bandwidth ranging into the low MHz.

The standard AED-200 consists of a daughterboard for the expansion interface on the C6x Evaluation Module. The full size daughterboard configuration includes voltage reference, digital buffers, regulators, programmable logic interface, and 90 pins of I/O connectors for off-board connections. The AED-200 comes with a manual, a demonstration FPGA logic configuration and example application program for the C6x DSP.

SIGNALWARE provides mounting services to convert the AED-200 into a custom prototype analog interface for a DSP based system. A/D and D/A converters along with the necessary filters and amplifiers are mounted as the board is assembled ensuring reliable, reflow soldering of surface mount components. SIGNALWARE also provides custom FPGA programs to configure the digital interface to the DSP.

Programmable DSP I/F Adds Performance

Preprocessing of the A/D samples and control of the converters with the Field Programmable Gate Array (FPGA) significantly reduces the load on the DSP making more computation possible with a single C6xxx DSP. A Xilinx SPARTAN^TM XCS20XL FPGA with 20,000 logic gates (1120 flip-flops, 12K RAM bits) is standard, and larger FPGAs are available as options. Serial flash memory (optional), socketed PROM or the JTAG port can provide FPGA configuration.

Surface Mount Breadboard Adds Flexibility

To make the analog interface to the board convenient and flexible, almost 7 sq. in. of breadboard space is provided. The analog interface to the converters always needs to be tailored to the application. No approach is more flexible than a breadboard area specifically designed for surface mount and through-hole analog ICs. The AED-200 breadboard accommodates wide and narrow SOICs (50 mil pitch) as well as 0.3 and 0.6 DIPs (100 mil pitch). By keeping the signal conditioning circuits on the board with the converters, noise, errors, and cost are reduced. Regulated +/- DC analog power buses supply the breadboard area.

Flash Memory Adds Stand-alone Capability

The AED-200 may have optional flash memory for C6x program and data storage on main boards without flash memory. Lack of boot up memory is often the critical factor in using the EVM boards in stand-alone mode. Either a 512 Kbyte or 1 Mbyte option is available.

Configuration Tables

The following tables determine the converter parts that can coexist in the mixed signal mounting area of one board. The sum of the Positions Required column of the table entries for the devices must be less or equal to 42. The AED-200 has a "piggy back" option that allows it to be used with other daughterboards to assemble complex prototypes.

Many other types of devices, e.g. RS422/485 transceiver (SN75ALS180), can be mounted in the mixed signal area beside those in the tables. The devices must have SOIC or wide SOIC packages. Pins may be connected to digital or analog grounds and power supplies, reference voltages, 42 FPGA I/O pins, and 16 analog connections to the breadboard area. Most connections are made with 0603 size surface mount components; few if any wires are required.

See the AED-200 Mounting Notes for more detail.

Note: * Analog performance may be limited to less than the full rated bandwidth by lead lengths inherent in the mixed signal mounting area.

Note: * Analog performance may be limited to less than the full rated bandwidth by lead lengths inherent in mixed signal mounting area.

AED-200 Specifications

Digital Interface to EVM/DSK:

• Xilinx Virtex^TM or SPARTAN^TM FPGA
• Full speed interface with EVM memory, serial ports, interrupts, DMA, and clocks.

Debugging Interfaces:

• JTAG - 14 pin FPGA and configuration flash memory

Digital I/O and External Synchronization:

• 24 - Buffered TTL Input/Outputs up to 100 MHz
• Switchable to input or output in groups of 8.

Operating Temperature Range: 0 to 40 degree C

Power: +5, +3.3, +/-12 VDC

Size: 191 mm L x 86.2 mm W x 13.8 mm D

Net Weight: 0.14 (0.31) kg (lb)

Ordering Information

AED-200 Analog Expansion Daughterboard* $ 695

Opt. 1a - 512 Kbyte Boot Flash Memory $ 125

Opt. 1b - 1.0 Mbyte Boot Flash Memory $ 155

Opt. 1c - Stacking Interface Connectors** $ 80

Opt. 1d - High Power 2.5V Supply** $ 95

Opt. 2g-4/6 - XCV50-4/6* FPGA Substitution $ 130/185

Opt. 2a-4/6 - XCV100-4/6 FPGA Substitution $ 205/310

Opt. 2b-4/6 - XCV150-4/6 FPGA Substitution $ 240/3700

Opt. 2c-4/6 - XCV200-4/6 FPGA Substitution $ 290/450

Opt. 2d-4/6 - XCV300-4/6 FPGA Substitution $ 420/670

Opt. 2e-4/6 - XCV400-4/6 FPGA Substitution $ 585/935

Opt. 2f-4/6 - XCV600-4/6 FPGA Substitution $ 940/1530

Opt. 2h-4/6 - XCV800-4/6 FPGA Substitution $ 1380/2255

Opt. 2t - XCS30XL-4* FPGA Substitution $ 75

Opt. 2u - XCS40XL-4 FPGA Substitution $ 85

Opt. 3a - A/D - D/A Custom Mounting $ 15 per Required Position

Opt. 3b - Buffer Amplifier $ 50 per Channel

Opt. 3f - Custom Analog Filters Call for Quote

Opt. 4a - A/D FPGA Test Configuration $ 300 per Device Type used on board(s)

Opt. 4b - D/A FPGA Test Configuration $ 200 per Device Type used on board(s)

Opt. 4 - Custom FPGA Configuration Call for Quote

* Requires only low cost Xilinx Foundation Basic (not ISE) for programing. Other FPGA substitutions require Standard tools.

** Stacking Interface Connectors and High Power 2.5V Supply options are mutually exclusive.

Quantity Pricing:

• Quantity of 2 or more identical - 10% off on board and options
• Quantity of 4 or more identical - 15% off on board and options
• Quantity of 10 or more identical - 20% off on board and options

Pricing subject to change without notice.

Delivery 20 working days subject to availability of optional FPGAs.

Terms:

• VISA or MasterCard
• Prepaid - 4% Discount (Check or Wire Transfer)
• COD - 2% Discount + $10 COD fee (US only)

Orders within USA and over $2500 with pre-approved credit:

• Net - 30 day
• 2% discount - 10 days
• Over 30 days - 1.5% per month from invoice date

Wire Transfer Fees - $10 plus fees charged by intermediate banks.

Warranty:

• Limited 90 day parts and labor (except FPGA) - details
• FPGA warranty as provided by manufacturer

Shipping and Handling:

• Shipping from Colorado Springs paid by customer.
• Standard shipping UPS Blue - 2 day
• Optional shipping UPS Red - 1 day
• Other forms of shipment in USA - $20 handling charge
• Orders outside USA - $20 to $100 handling charge depending country

For information on other daughterboards, see our Summary of Signalware Daughterboards.

For information on DSP Development boards that use Signalware daughterboards, see our Summary of DSP Development Products.

For information on various combinations of TMS320C5x/C6x EVM and DSK products listed above with the Signalware daughterboards, see our Prototype Configuration Table.

See SIGNALWARE's Home Page or Customer Reply Form for further assistance.