TMS320C5x/C6x EVALUATION MODULE
Analog Expansion Daughterboard
AED-150 Long Signal Memory
TMS320C5x/C6x EVALUATION MODULE
Analog Expansion Daughterboard
AED-150 Long Signal Memory
See SIGNALWARE's Home Page or Customer Reply Form for further assistance.
PRELIMINARY DATA SHEET
Product Available for 4th Q 2002
The SIGNALWARE AED-150 Long Signal Analog Expansion Daughterboard for the Texas Instruments TMS320C5x/6x Evaluation Module and Starter Kits provides a way to collect or generate signals at faster rates than the DSP can process I/O. The AED-150 has a burst mode SDRAM capable of storing 4 gigabytes of data. The memory is arranged as four slices of 16-bit samples up to 512 M samples (M=1024*1024) in each slice. The board also has up to four A/D or D/A devices (total) which may operate in as fast as 50 MS/s (samples per second). This provides about 10 seconds operating time at 50 MS/s. This can be extended by running slower or using fewer devices. Data can be read or written by the DSP in 64 K byte blocks at the full rate of the DSP EMIF bus (from 20 to 80 M bytes per second depending of DSP target board). The board has four DIMM sockets (168 pin) which may have up to four 133 MHz DIMM modules with 128 M bytes to 1 gigabyte each. An FPGA provides a flexible (configurable) interface to the SDRAM, to the converters, and to the DSP.
The board may be configured one of four ways: For Signal Generation, samples pre-stored in SDRAM are transferred to D/A converters sequentially in real time. The signal may then repeat. For Data Collection, the A/D converters transfer samples to the SDRAM in real time which the DSP reads for processing at a slower rate. For Extended Memory, the board contains only memory which may be transferred to and from the DSP with a DMA in blocks sequentially. For Delay Line, where an analog signal is read with an A/D, stored for up to several seconds digitally, and then converted back to an analog signal with a D/A. Delay Line operates at reduced sample rates.
The standard AED-150 consists of a daughterboard for the expansion interface on the C5x/6x Evaluation Module or Starter Kit. The extended size TI standard daughterboard includes Xilinx XCV100E FPGA, 4 DIMM sockets, up to 4 A/D or D/A converters, and up to 8 SMB coax connectors. The AED-150 comes with a manual, a demonstration FPGA logic configuration and test program for one DSP target board.
The AED-150 may have 512 Kbyte or 1 Mbyte optional flash memory for DSP program and data storage for use on main boards without any or adequate flash memory. This flash may be used to boot the DSP in standalone mode.
Configurable DSP I/F Adds Flexibility
The Xilinx field programmable gate array (FPGA) on the daughterboard allows the AED-150 to be configured in many different operating configurations. It provides an interface to the DSP through the expansion memory connector and the EMIF bus. The properties of this bus varies on different DSPs, but the FPGA can bridge those differences to make an efficient data transfer mechanism. The FPGA controls the sample rates and timing of the data converters. Most important is the control of the SDRAM. This memory must be refreshed interleaved with the burst transfers of data to and from the memory to other devices. The FPGA allows for different sized DIMM modules to be used and different ways to use the 16 bit slices for driving the data converters. The user may configure the FPGA using the Xilinx tools, or custom configurations may be purchased from Signalware. The configuration is stored in a flash memory on the board which is reprogrammed via a JTAG cable connector.
AED-150 Specifications
Data Converters: (Total of 4 Converters Maximum)
SDRAM Memory:
Interfaces:
Digital Interface to EVM/DSK:
Xilinx SpartanTM 208 pin or Virtex-ETM 240 pin FPGA - Full speed EMIF bus, interrupts, DMA, and clocks.
Debugging Interfaces:
JTAG - 14 pin FPGA and configuration flash memory
Optional Features:
Operating Temperature Range: 0 to 40 degrees C
Power:
Size: 230 mm L x 86.2 mm W x 13.8 mm D
Net Weight: 0.2 (0.5) kg ( lb.)
Ordering Information (AED-150 Options)
* Free configuration tools available from Xilinx (WebPack). Other FPGAs require purchased tools.
** Stacking Interface Connectors and High Power 1.8V Supply options are mutually exclusive. Stacking connectors are required when more than one board is used on a single DSK or EVM. The High Power may be mounted on the outer most daughterboard, and it may supply FPGAs on more than one daughterboard. High Power 1.8V Supplies are recommended for all FPGA options XCV300E-8 and above.
Pricing and Delivery:Please complete a Request of Quotation form. Your request will be processed for direct purchase from Signalware or forwarded to the appropriate distributor.
Terms and Conditions: Contact distributor except for direct purchase.
For information on other daughterboards, see our Summary of Signalware Daughterboards.
For information on DSP Development boards that use Signalware daughterboards, see our Summary of DSP Development Products.
For information on various combinations of TMS320C5x/C6x EVM and DSK products listed above with the Signalware daughterboards, see our Prototype Configuration Table.
See SIGNALWARE's Home Page or Customer Reply Form for further assistance.