SIGNALWARE LOGOTI DSP LOGO

TMS320C5x/C6x EVALUATION MODULE

Analog Expansion Daughterboard

AED-101 (70/80 MHz, 2 In, 2 Out)

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AED-101 Wide BandDaughterboard

DATA SHEET

The SIGNALWARE AED-101 Wide Bandwidth Analog Expansion Daughterboard for the Texas Instruments TMS320C5x/6x evaluation products provides an economical way to build an RF signal processor or software radio transceiver. The daughterboard has two 2-channel A/D converters and two D/A converters. The input bandwidth is 1.0 GHz which allows direct conversion of RF signals by undersampling. The D/A output channels may be updated simultaneously. Six buffer amplifier and 4 transformer positions provide a variety of input-output and signal conditioning options. In addition to analog channels, 16 buffered digital signals are available in two configurations. Breadboard space provides for signal conditioning and interface circuits. The AED-101 has application in software radio, RF simulators, image sensor processing, and communications.

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The AED-101 is ideally suited to prototyping systems with TI C5x and C6x Digital Signal Processors (DSP). A wide variety of TI DSP devices can be evaluated or demonstrated by combining TI prototyping products with this daughterboard. The analog circuit prototyping for signal conditioning is conveniently built with specialized analog and breadboard areas on the daughterboard. The digital interface to the DSP is accomplished with a Field Programmable Gate Array (FPGA). This approach to prototyping can significantly reduce time-to-market.

Also, the AED-101 may be used to construct inexpensive personal computer based or standalone systems where the number of systems does not justify a custom designed board. RF test sets and instrumentation are examples of low volume wide band DSP applications.

The standard AED-101 consists of a daughterboard for the expansion interface on the C5x or C6x Evaluation Modules or DSP Starter Kits. A TI standard full-size daughterboard configuration includes 2-A/D, 2-D/A, voltage reference, 16 digital I/O, regulators, programmable logic interface, a 40-pin digital I/O connector, and four SMB RF connectors for off-board connections. Additional options include analog buffers, transformers, four more SMB connectors, and flash memory for DSP program storage available in either 512 Kbyte or 1 Mbyte. The digital I/O may be configured as: 4 input, 4 output and a group of 8 that can be switched to either input or output, or as two switchable groups of 8. The AED-101 comes with a demonstration logic program and software for the DSP.

Programmable DSP I/F Adds Performance

Preprocessing of the A/D samples and control of the converters with the FPGA significantly reduces the load on the DSP making more computation possible with the DSP. A Xilinx Virtex-ETM XCV150E-6 FPGA with approximately 71,000 system gates is standard, and larger Virtex-ETM FPGAs are available as options. Serial flash memory or optional socketed, serial PROM provide FPGA configuration.

Surface Mount Breadboard Adds Flexibility

To make the analog interface to the A/D and D/A converters convenient and flexible, 3 square inches of breadboard space for surface mount and through-hole analog ICs is provided. The AED-101 breadboard accommodates wide and narrow SOIC (50 mil pitch) packages as well as 0.3 and 0.6 DIPs (100 mil pitch). By keeping the application specific signal conditioning circuits on the board with the converters, noise, errors, and cost are reduced. The breadboard area is supplied with regulated +/- DC analog power voltages, and 4.096, 2.048 and 1.024 reference voltages.

AED-101 Block Diagram

AED-101 Specifications

Analog to Digital Conversion:

Digital to Analog Conversion: Voltage Reference Digital Interface to EVM:

Xilinx Virtex-ETM FPGA - Full speed interface w/ EVM memory, serial ports, interrupts, DMA, & clocks.

Debugging Interfaces:

Digital I/O and External Synchronization: Operating Temperature Range: 0 to 40 deg C

Power: +5, +3.3, +/-12 VDC

Size: 191 mm L x 86.2 mm W x 13.8 mm D

Net Weight: 0.14 (0.31) kg ( lb)

Ordering Information

AED-101 Analog Expansion Daughterboard
Opt. 1a - 512 Kbyte Boot Flash Memory
Opt. 1b - 1.0 Mbyte Boot Flash Memory
Opt. 1c - Stacking Interface Connectors**
Opt. 1d - High Power 1.8V Supply**
Opt. 1e - 80 MHz Upgrade (ADS809)
Opt. 1o - xx.xx MHz Oscillator
Opt. 1t - Digital I/O - 4 In / 4 Out / 8 Bidirectional
Opt. 2g-8 - XCV50E-8* FPGA Substitution
Opt. 2a-6/8 - XCV100E-6/8* FPGA Substitution
Opt. 2c-6/8 - XCV200E-6/8* FPGA Substitution
Opt. 2d-6/8 - XCV300E-6/8* FPGA Substitution
Opt. 2e-6/8 - XCV400E-6/8 FPGA Substitution
Opt. 2f-6/8 - XCV600E-6/8 FPGA Substitution
Opt. 2h-6/8 - XCV1000E-6/8 FPGA Substitution
Opt. 3f - Custom Analog Filters
Opt. 3t - I/O Transformers
Opt. 4 - Custom FPGA Configuration

* Free configuration tools available from Xilinx (WebPack). Other FPGAs require purchased tools.

** Stacking Interface Connectors and High Power 1.8V Supply options are mutually exclusive.  Stacking connectors are required when more than one board is used on a single DSK or EVM.  The High Power may be mounted on the outer most daughterboard, and it may supply FPGAs on more than one daughterboard.  High Power 1.8V Supplies are recommended for all FPGA options XCV300E-8 and above.

Pricing and Delivery:Please complete a Request of Quotation form. Your request will be processed for direct purchase from Signalware or forwarded to the appropriate distributor.

Terms and Conditions: Contact distributor except for direct purchase.


For information on other daughterboards, see our Summary of Signalware Daughterboards.

For information on DSP Development boards that use Signalware daughterboards, see our Summary of DSP Development Products.

For information on various combinations of TMS320C5x/C6x EVM and DSK products listed above with the Signalware daughterboards, see our Prototype Configuration Table.

See SIGNALWARE's Home Page or Customer Reply Form for further assistance.