

TMS320C5x/C6x EVALUATION MODULE
Analog Expansion Daughterboard
AED-100 (40/80 MHz)
See SIGNALWARE's Home Page or Customer Reply Form for further assistance.
The SIGNALWARE AED-100 High Speed Analog Expansion Daughterboard for the Texas Instruments TMS320C5x/C6x Evaluation Modules (EVM) and DSP Starter Kits (DSK) provides an economical way of building a "software radio" (transceiver using primarily digital circuitry controlled by software) . The daughterboard has dual channel A/D and D/A converters that can directly sample radio frequencies (RF) up to 75 MHz (700 Mhz on the AED-100B) with bandwidths approaching 20 MS/s (40 MS/s on the AED-100B) for single channel using undersampling techniques . Breadboard space is provided for constructing RF up/down conversion circuits. The AED-100 is ideally suited to constructing digital cellular radios for operation with CDMA, GSM, and IS-136 (TDMA) systems. Handling the high sample rates is made easy by the programmable interface between the converters and C6x Digital Signal Processor (DSP) on the target board (EVM or DSK). The AED-100 is an excellent DSP analog interface for many other high speed applications.

The standard AED-100 consists of a daughterboard for the expansion interface on the C6x Evaluation Module. The full size daughter board configuration includes 2-A/D, 2-D/A, amplifiers, regulators, and a programmable logic interface. The AED-100 comes with a demonstration logic program and software for the C6x DSP. Actual operating frequencies depend on the target board chosen, choice of oscillator option and the preprocessing performed before transmitting the data to the DSP on the target board.
Programmable DSP I/F Adds Performance
High speed preprocessing of the A/D samples with the Field Programmable Gate Array (FPGA) significantly reduces the load on the DSP making many high performance applications possible with a single C6xxx DSP. On the AED100, a Xilinx XC4013XLA-09* FPGA with approximately 13,000 logic gates is standard, and larger FPGAs are available as options. A socketed, serial PROM provides FPGA configuration. On the AED100A, choice of the Spartan and Virtex FPGAs are available. On the AED100B, choice of the Spartan and VirtexE FPGAs are available.
The FPGA on the AED-100 in conjunction with the optional phase-locked loop controlled VCO provides a wide variety of fast clock frequencies for A/Ds and D/As that are synchronized with the CPU clock. The Virtex FPGAs on the AED-100A/B provide a similiar capability with the build in DLL.
Surface Mount Breadboard Adds Flexibility
To make the analog interface to the board convenient, flexible, and high performance, over 7 sq. in. (3 sq. in. on the AED-100B) of breadboard space is provided. The analog interface to the A/D and D/A converters always needs to be tailored to the application. No approach is more flexible than a breadboard area specifically designed for surface mount and through-hole analog ICs. The AED-100/A/B breadboard accommodates wide and narrow SOICs (50 mil pitch) as well as 0.3 and 0.6 DIPs (100 mil pitch). By keeping analog interface circuits on the board with the converters, noise and offset are reduced. 6-SMB connector footprints adjoin the area at the board edge. Regulated +/- DC analog power buses supply the breadboard area.
Flash Memory Adds Stand-alone Capability
The AED-100 has optional boot flash memory for C6x program storage. Lack of boot up memory is often the critical factor in using the EVM in stand-alone mode. Either 512 Kbyte or 1 Mbyte option is available. This is separate from and in addition to the configuration SPROM or flash provided for the FPGA.
AED-100 Specifications
Analog to Digital Conversion:
2- TI TLC5540 Data Converters (AED-100 and AED-100A)
2- TI TLV5580 Data Converters (AED-100B only)
2 - TI THS3001 Wide band input amplifier (AED-100 only)
2 - TI THS4062 Wide band output amplifier (AED-100A and AED-100B)
Digital to Analog Conversion:
2 - TI TLC7524 Data Converters (AED-100 only)
2 - TI THS5641 Data Converters (AED-100A and AED-100B)
2 - TI THS4001 Wide band output amplifier (AED-100 and AED-100A)
2 - TI THS3001 Wide band input amplifier (AED-100B only)
Sampling Clock:
TI
TLC2933 Phase-locked Loop
(optional on AED-100 only)
External Oscillator 10-80 MHz (optional on AED-100B only)
Digital Interface to EVM:
Digital I/O and External Synchronization:
Debugging Interfaces:
Operating Temperature Range: 0 to 40 degree C
Power: +5, +3.3, +/-12 VDC
Size: 191 mm L x 86.2 mm W x 13.8 mm D
Net Weight: 0.14 (0.31) kg (lb)
Ordering Information
* Free configuration tools available from Xilinx (WebPack). Other FPGAs require purchased tools.
** Stacking Interface Connectors and High Power Supply options are mutually exclusive. Stacking connectors are required when more than one board is used on a single DSK or EVM. The High Power may be mounted on the outer most daughterboard, and it may supply FPGAs on more than one daughterboard. High Power Supplies are recommended for all FPGA options XCV300-6 and XCV300E-8 and above.
Pricing and Delivery:Please complete a Request of Quotation form. Your request will be processed for direct purchase from Signalware or forwarded to the appropriate distributor.
Terms and Conditions: Contact distributor except for direct purchase.
For information on other daughterboards, see our Summary of Signalware Daughterboards.
For information on DSP Development boards that use Signalware daughterboards, see our Summary of DSP Development Products.
For information on various combinations of TMS320C5x/C6x EVM and DSK products listed above with the Signalware daughterboards, see our Prototype Configuration Table.
See SIGNALWARE's Home Page or Customer Reply Form for further assistance.